The Internet of Things is promising as it drives the datafication of our everyday life and thus, leverages synergies between originally considered “dead” things and enables them to proactively serve humans. IoT5.0, an Artificial Intelligence assisted Internet of Things, could even more benefit society, as the devices could even learn how to provide more value. But the ubiquitous connectivity comes at a cost. Security levels have to rise tremendously to ensure a network stays secure and safe for humans. This additional effort often is a burden for small and medium sized enterprises as the complexity and security demands of such systems rise faster than available resources. Consequently., RESILIENT TRUST focuses on end-to-end security of IoT processing chains with a focus on strong exploitation for SMEs. Moreover, RESILIENT TRUST will address and significantly mitigate the major risks to enable IoT 5.0. That way., this project will be a driver for sustainable development and the generation of convenience and wealth. A solution is proposed to ensure end-to-end security by boosting RESILIENCE and TRUST along different key supply chains of IoT device.

Energy efficiency is of utmost importance in modern applications. Power consumption optimisation could be improved by a comprehensive analytical modeling of the characteristics of critical blocks in a system. Dynamic range (DR) has a strong effect on the power consumption of analog circuits, and is determined by circuit non-linearity and noise level. Noise is well modelled even in deep sub-micron technologies, yet there is a lack of analysis and modeling of the non-linearity. An analytical MOSFET differential pair non-linearity model is presented in this work. The proposed model is universal to a wide range of technologies from long to ultra-deep sub-micron devices, and is valid for all operating regions as it is based on the EKV MOSFET model. Furthermore, a model including drain-voltage-induced non-linearity is also developed, and a concise 3dB input intercept point (IIP3) formula incorporating the drain induced non-linearity in terms of the voltage gain is presented. The proposed models are validated with DC and AC simulations and measurements.

Power consumption is of utmost importance in portable devices as they are operated from a limited energy supply. Wireless radio is one of the most power-hungry blocks in these systems and needs to be activated opportunistically. Radio frequency (RF) spectrum sensing can be performed with a dedicated low power radio to control the main wireless radio. A low power receiver architecture is proposed in this work to monitor the 2.4GHz Industrial, Scientific, and Medical (ISM) band for communication standards such as Wireless Local Area Network (WLAN), Zonal Intercommunication Global-standard (ZigBee), and Bluetooth-Low-Energy (BLE). The whole ISM band is down-converted to zero-intermediate-frequency (ZIF) and a tunable base-band complex band-pass filter (CBPF) is used to scan the spectrum. A widely tunable first order ultra-low-power transconductor-capacitor (Gm-C) CBPF architecture was designed and fabricated in GF 22FDX technology, which occupies 0.0049mm 2 area. A frequency shift of ±60MHz was achieved with 5-40MHz bandwidth range. Power consumption ranges from 6.7$\mu \text{W}$to 99.2$\mu \text{W}$with the best and the worst figure-of-merit of 0.034fJ/pole and 0.082fJ/pole that is the energy consumption per pole normalized by the spurious free dynamic range.

Audio processing had been in demand throughout the electronic era. Recent advances in neural networks increased the demand on audio processing for speech recognition applications. In this work, a rigorous study on the dynamic range and system complexity optimization is presented for a mixed-signal keyword spotting system. The proposed system consists of an analog feature extractor and a neural network based keyword classifier. The results showed that with the proposed method, more than an order of magnitude power saving can be achieved in the analog feature extraction compared to the digital state-of-the-art counterpart.

Bluetooth Low Energy (BLE) has been designed as a power efficient protocol for small portable and autonomous devices, showing its efficiency for connecting these devices with smartphones to periodically and frequently exchange data, like heart rate or notifications. Additionally, BLE is present in almost every smartphone, turning it into perfect ubiquitous remote control for smart homes, buildings or cities. Nevertheless, there is still room to improve BLE performance for typical IoT use cases where battery lifetime should reach several years. In this paper we propose an extension to a model for evaluating BLE performance, latency and energy consumption, in order to provide realistic results based on various scenario conditions. In addition, we propose a parameter optimization of the BLE Neighbor Discovery process, in order to obtain the best performance possible depending on the constraints of specific use cases. Our results on two typical IoT test-cases show that advertiser battery lifetime can be increased up to ~89x (9.55 days to 2.32 years) for a first case, and ~281x (9.55 months to 7.36 years) for a second case.

Bluetooth Low Energy (BLE) has shown higher energy efficiency and robustness than other well known Wireless Sensor Network (WSN) protocols, making it a strong candidate for implementation in IoT scenarios. In addition, BLE is in almost every smartphone, turning it into perfect ubiquitous remote controls for smart homes, buildings or cities. In this paper we propose new operating modes for BLE to provide a much wider applicability range covering asynchronous, aperiodic and very low frequency scenarios while extending lifetime, without modification of the existing BLE specification. In order to estimate battery lifetime, we propose a coin cell battery model. We show how to efficiently adapt the protocol for different IoT scenarios based on their requirements, thus extending battery lifetime as much as possible while guaranteeing acceptable latency. Our results on two typical test-cases show that by using an optimized configuration and appropriate operating mode based on scenario requirements, lifetime can be increased up to ≈2× (4.1 to 7.3 years) for a BLE master in a first case, and ≈ 58× (3.05 months to 14.82 years) for a BLE slave in a second case. This shows BLE compatibility with a vast amount of IoT-related use cases.

This paper presents the design of an Ultra Low Power (ULP) inductorless Low Noise Amplifier (LNA) based on a Common Gate (CG) architecture using the back gate control of the Fully-Depleted Silicon-On-Insulator (FDSOI) technology. It demonstrates the potential of the back biasing to lower the power consumption of more than 30 % compared to a design without back biasing, while keeping similar performance. This paper also shows the possibility with the back gate control of this technology to reach additional performance, suitable for the design of tunable LNAs. The proposed LNA has been implemented in ST-Microelectronic 28 nm FDSOI Technology and its active area is only 0.0015 mm2. The measured performance exhibit more than 16 dB of voltage Gain (Gv), 7.3 dB of Noise Figure (NF) and an Input referred third-order Intercept Point (IIP3) of -16 dBm. The total power consumption is 300 μW from a 0.6 V supply. The same LNA reached other performance modes at constant Figure of Merit (FoM).

This paper is devoted to the yield optimization of the radio-frequency (RF) front-end of wireless receiver. The yield together with the circuit performances are often sensitive to the choice of parameters of its components and blocks, and can be improved at circuit design level. However, it is better evaluated when considering the whole receiver at system level. For this purpose, we first use a design of experiment (DoE) technique to generate meta-models of the building blocks. Then, we apply a version of the stochastic gradient method to find a good approximation of the optimum for the circuit yield.

In nanoscale integrated circuit technologies, process parameter fluctuations gain increasingly in importance. Efficient methods are thus required during the design phase to evaluate the resulting variability. In this letter, we propose a new method to estimate the variation bounds of analog circuit performance. This method combines design of experiment techniques with the Cornish-Fisher expansion: process parameter variations are first mapped to circuit performance metrics by a quadratic model, and then an analytical approximation of the performance distribution's quantiles enables the enclosure of the performance variations. The proposed method demonstrates a better accuracy/efficiency ratio than Monte-Carlo-based methods.

In this paper a novel solution for coherent combination in ultra wide band (UWB) beamformings for real time locating systems (RTLS) is proposed. The architecture uses a double quadrature receiver and the time alignment is approached by digital phase-shifters. A comparison and evaluation with classical True Time delay (TTD) architectures is presented. Our proposed architecture achieves same performances than the TTD approach, showing that complex TTD modules could be replaced advantageously by a single base-band digital phase shifters. Moreover, our solution does not need higher sampling rates that make it suitable for low power consumption.

The benefits of adaptive power reconfigurability in WPAN receivers are investigated. The analysis is based on a direct-conversion IEEE 802.15.4 receiver and is focused on the analog baseband block. High-level power models are built for the baseband filter and the ADC which are, then, optimized for minimum total power dissipation to decide on the reconfiguration strategy. The optimum is reached with a first-order filter together with an ADC that is reconfigurable between 21.0 dB and 69.8 dB (corresponds to 3.2-bit and 11.3-bit ENOB). An illustrative operating schedule is derived to evaluate the possible power reduction that can be obtained through adaptive power reconfigurability. In the end, it is found that the average power dissipation can be reduced from 602 μW to 24.1 μW by using a power-reconfigurable ADC, which corresponds to a reduction by a factor of 25 (14 dB).

A multiplying D/A converter stage incorporating a novel technique for compensating the residual error due to finite amplifier gain is proposed. The scheme is suitable for deep-submicron CMOS technologies and is advantageous compared to the available correlated double sampling techniques because it neither doubles the size of the sampling capacitance, nor requires processing of the same input signal twice for cancelling the residual error at the virtual ground. The conducted behavioral simulations confirm the efficiency of the proposed technique applied to a pipelined A/D converter.

We present a method to automatically match a system to the load variation accurately with a very short matching time for Ultra Low Power medical applications. A demonstrator was fabricated and an experimental set-up in the Medical Implant Communication System (MICS) frequency band of 402–405MHz was realized including a pacemaker antenna prototype immersed on a homogeneous lossy liquid. The matching network consists of a low pass π structure with tunable components made of varactors. Methodologies for simplifying the matching network design are introduced. The measurements show that a S11 up to −30dB is obtained with a matching time of 900µs.

This paper proposes a method to introduce BAW resonators in the loop of a continuous-time sigma-delta modulator. The method is based on the equivalence between the noise-transfer-function of a conventional bandpass discrete-time sigma-delta and the noise-transfer-function of a continuous-time BAW-based sigma-delta modulator with FIRDACs. The method is general and can be applied to BAW resonators with and without cancellation of the anti-resonance frequency. The noise-transfer-function and the signal-transfer-function of the BAW-based sigma-delta modulator are analyzed and compared with their discrete-time counterpart.

To enable an efficient implementation of multiple-antenna OFDM systems, this paper proposes an approach to reduce the influence of transmitter-induced nonlinearities in such systems. The approach comprises a preamble design, an estimation method and a digital compensation algorithm. Correction for the nonlinearities of the different transmitter branches is applied in the receiver, which requires no extra hardware. A numerical performance evaluation shows that the proposed approach can successfully be applied with minimal performance degradation compared to non-impaired systems.

In this paper, the problematic of co-design between LNA and antenna is addressed. The targeted application is ultra wide band where this part of front end is a main interest in RF design. A comparison is drawn out between a 50 Ohm and a co-designed version, with same LNA architecture and power consumption. Simulation results show a 7 dB power gain enhancement in the latter version. Noise factor is improved by more than 1.5 dB over the whole bandwidth

Multi carrier communication systems are very sensitive to phase noise caused by oscillator at the receiver front-end. This paper presents a new approach for evaluating the degradation introduced by phase noise on a MC-CDMA receiver. Using the random matrix theory, a new analytical model of signal to interference plus noise ratio (SINR) has been developed. It is validated thanks to link level simulation based on behavioral phase noise models. Moreover, it allows us to derive a new weighting function, analog as the one proposed by Stott for OFDM systems (1998). This weighting function is very interesting for RF engineer when they design the receiver frequency synthesizer

Owing to their higher output dynamic two-stage amplifiers may become an interesting alternative to cascaded single-stage amplifiers for low voltage switched capacitor applications.Therefore, a comparison of the minimum power consumption of both approaches, based on an optimisation methodology, is presented.It is worked out, which amplifier type should be used to achieve minimum power consumption for a given supply voltage, capacitor ratio and desired settling precision.