Good-Die-in-Bad-Neighborhood (GDBN) is a technique employed to identify chips that pass initial tests but may have defects. Previous research used neural networks and expanded observation windows but ignored the impact of isolated dice. This paper improves wafer pattern information through denoising and creates a lightweight model. It also reduces training time by annotating multiple dice simultaneously. Experiments on real-world datasets show the model effectively captures more Test Escapes, reducing Defective Parts Per Million (DPPM) and improving return merchandise authorization gains.

Good-die-in-bad-neighborhood (GDBN) is a widely adopted method utilizing the fact that manufacturing defects tend to exhibit spatial dependency and form a cluster or specific pattern of bad dice on a wafer. Existing research studies on GDBN mainly focus on learning such spatial relationships within a limited observation window through simple mechanisms such as linear regression or multilayer perceptron model. In this paper, we propose MetaFormer-GDBN, a transformer-based deep learning model with the observation window extending to the entire wafer to include broader pattern information. The enhanced neighboring information and model capacity allow our method to capture more complex patterns of bad dice. Experiments show that compared to previous work, our method can achieve up to 50 % performance improvement, reducing the DPPM (defective parts per million) with minimal yield loss.

With the increasing demand for high reliability of products, how to prevent potential defective devices from shipping to customers is a serious issue about which more and more companies are concerned. Toward this end, many test methods have been developed to screen out outliers. However, basic statistical paradigm may not be enough to handle the shrinking transistor size and increasingly complex circuit design. In this paper, we propose to use the concept of Z-score derived from our proposed neural network, called single density network (SDN), to define level of abnormality. We also define new metrics called self-excluded fail rate (SE fail rate) and normalized area under curve (AUC) to be our criteria to quantify and further visualize the outcome. To filter out spatially-correlated outliers, we make use of specific information of neighboring dice and encode them into our input features for the proposed SDN. A series of experimental results on industrial data reveal the effectiveness of our methodology and the better ability to identify defective outliers than existing conventional statistical approaches for a variety of analog tests.

A defect-based bridge fault represents the faulty behavior of an interconnect short defect obtained by SPICE simulating the two shorted cells with the short defect injected. In this article, we have developed a framework to automatically extract defect-based bridge faults and utilize commercial automatic test pattern generation (ATPG) to generate corresponding test patterns for a given design. A defect-based bridge fault model can not only describe the faulty behavior of a short defect precisely but also result in collapsible faults at one shorted cell pair. As a result, using a defect-based bridge fault model for ATPG can lead to a significantly smaller bridge-fault test set when compared with a conventional four-way dominance bridge fault model, where four noncollapsible faults at one shorted cell pair are considered for ATPG. In addition, some short defects can only be detected by the test set for defect-based bridge faults but not by the test set for four-way dominance bridge faults with more test patterns. The runtime required for extracting 1-time-frame (1tf) defect-based bridge faults has been proven acceptable on industrial designs and some techniques were also proposed to speed up the runtime for extracting 2tf defect-based bridge faults. All experiments in this article are conducted based on industrial designs.

A defect-based bridge fault represents the faulty behavior of an interconnect short defect obtained by SPICE-simulating the two shorted cells with the short defect injected. In this paper, we have developed a framework to automatically extract defect-based bridge faults and utilize commercial ATPG to generate corresponding test patterns for a given design. Defect-based bridge fault model can not only describe the faulty behavior of a short defect precisely but also result in collapsible faults at one shorted cell pair. As a result, using defect-based bridge fault model for ATPG can lead to a significantly smaller bridge-fault test set when compared to conventional 4-way dominance bridge fault model, where four non-collapsible faults at one shorted cell pair are considered for ATPG. Also, some short defects can only be detected by the test set for defect-based bridge faults but not by the test set for 4-way dominance bridge faults with more test patterns. The experimental result based on industrial designs has demonstrated the effectiveness of using defect-based bridge faults for ATPG while showing an affordable runtime on extracting defect-based bridge faults.

Due to the temporal behavior of living cells, the microscopy sequences analysis is indeed a challenging task. Unet architectures are normally considered as one of the most powerful tool for segmentation of biomedical images. However, there is still no clear way to deal with the temporal and spatial characteristics of the time-series cell images. This study uses the weight pre-trained on a large scale of data as initial weights and Convolutional Long Short Term Memory (CLSTM), which replace most of the pure convolution operation in the original Unet, to obtain better performance than many significant network. We compared eight UNet encoder network architectures: VGG11, VGG13, VGG16, VGG19, Resnet18, and Densenet121, Inceptionv3 and Incetionresnetv2. Among all the networks, it is the architecture of VGG13 that obtain the best segmentation results on testing data (a public available data set). We then evaluated the performance of these models with multiple training, validation and testing. Two evaluation methods (intersection over union, IoU and Error metrics) are adopted to solidify the work of the improvement. In this paper, we firstly discovered the most powerful structure for encoder of Unet through plentiful experiments and comparison of multiple deep learning models. Secondly, we further successfully enable the best model to perform spatiotemporal encoding. For evaluation, the comparison with other significant Unet-based and FCN-based network are made eventually.

At speed Built-In Self Test (BIST) circuit can solve many test challenges generated from traditionally slower Automatic Test Equipment (ATE). In this paper, a double edge clipping technique is proposed for built-in at-speed delay testing requirements. It differs from traditional circuit delay testing techniques by changing the clock rate using external ATE. This method uses lower-speed input clock frequency, then applies internal BIST technique to adjust clock edges for circuit at-speed delay testing and speed binning. Test chips are fully validated. The fine-scale (16ps) progressive capture edge adjustment technique with high-precision (28ps) calibration circuit is effective for at-speed delay testing and performance binning.

A double edge clipping technique is proposed for at-speed BIST testing. It differs from traditional circuit delay testing techniques by changing the clock rate using external ATE. This method uses lower-speed input clock frequency, then applies internal BIST circuit to adjust clock edges for circuit at-speed delay testing and speed binning. This built-in at-speed delay test with calibration mechanism named as double edge clipping (DEC) technique. DEC is based on the lunch on shift (LOC) scheme by precisely controlling the launch and capture edges during delay test operation. Two wide-range (26% -80%), fine-scale (16ps) duty cycle adjustment circuits with high-precision (28ps) calibration mechanism are effective applied for at-speed delay testing and performance binning. The key to DEC testing technique is to generate a pair of clock pulses for the launch and capture events. Two DCPG provide adjusted positive clock edge during test operation. DEC uses 500kHz low speed input clock then provides working clock frequency from 197MHz to 932MHz.