Developing functional test programs for hardware testing is time-consuming and experience-wise. A functional test program’s quality is usually assessed only through expensive fault simulation campaigns during early development. This paper presents indirect quality measurements of fault detection capabilities of functional test programs to reduce the total cost of fault simulation in the early development stages. We present a methodology that analyzes the instruction trace generated by running functional test programs on-chip and building its control and dataflow graph. We use the graph to identify potential flaws that affect the program’s fault detection capabilities. We present different graph-based techniques to measure the programs’ quality indirectly. By exploiting standard debugging formats, we individuate instructions in the source code that affect the graph-based measurements. We perform experiments on an automotive device manufactured by STMicroelectronics, running functional test programs of different natures. Our results show that our metric allows test engineers to develop better functional test programs without basing their development solely on fault simulation campaigns.

The in-circuit test checks whether the board’s electrical and electronic components have been correctly soldered when producing printed circuit boards. When such a test is performed using a flying-probe tester, the cost of testing is mainly related to the time required for moving probes over the board and the time necessary for defining such movements, tuning the optimization on the number of devices that will eventually be tested. Since the 2000s, flying probe testing has been gaining popularity. Still, despite its industrial relevance, the research has been impaired by the lack of publicly available benchmarks for testing the new algorithms and comparing the different ideas. This paper presents an open test set of realistic boards, ranging from a few thousand to half a million test points, together with a tool for generating more samples. It also presents an optimizer for flying probe tests composed of two separate planners: one global detecting test that could be performed together and reordered to obtain a more efficient probing sequence, and one local, implementing the probe movements and taking care of specific board features. The test set will eventually be used to present a quantitative evaluation of the performance of the proposed approach.

Testing and validation check a hardware device or a software application against the desired design requirements. They are a vital part of all steps of system engineering and typically account for a significant percentage of the overall development cost. This paper presents a novel technique to provide a quick preliminary evaluation of functional test procedures of various natures, ranging from Software-Based Self-Test to Burn-In Functional Stress and System-level tests. We define a new metric called “connectivity”, which is fast to compute and can be used to guide functional program development. The method does not require logic or fault simulations, and it is based on the analysis of the execution trace generated by the functional program. To summarize our process, we first obtain the trace directly from the chip, running the software through a debugger. Then, we create a graph representation of the program data flow. Finally, we analyze the graph to identify instructions that negatively impact the final coverage. We perform experiments on an automotive device manufactured by STMicroelectronics, and we demonstrate the effectiveness of the approach in terms of computation time and beneficial effects on the fault coverage.

With the explosion of off-the-shelf SoCs in terms of size and the advent of novel techniques related to failure modes, commercial ATPG and fault simulation engines can often be insufficient to measure the coverage of very specific metrics. In these cases, many researchers firstly store the simulation trace during the analysis phase. Then, they collect the desired statistics during a post-processing step. In this framework, the so-called Value Change Dump (VCD) is a very commonly used file format to record simulation traces. The target of this paper is twofold. From the one hand, we illustrate some Burn-In (BI) related metrics which cannot be evaluated by current commercial fault simulators and ATPG engines. These metrics are indeed based on a post-processing analysis of memory dumps in VCD format. From the other hand, we mitigate the evaluation time and the memory required to analyze huge VCD files by exploiting optimization techniques coming from modern programming features and smart parallelization. Adopting this strategy, we can analyze simulation dumps of more than 250 GBytes in less than one hour, showing improvements of two orders of magnitude over previous tools, with a consequent higher scalability and testability power.

Cochlear implants partially restore auditory sensation in individuals affected by severe to profound hearing loss. We investigated vowel detection, identification, and discrimination in a group of congenitally-deafened, unilaterally-implanted, Italian children and in a group of age-matched controls, by combining behavioral and neurophysiologic measures. Comparable vowel identification and discrimination performance emerged for cochlear-implant and normalhearing children at the behavioral level. At the neurophysiologic level, on the other hand, cochlear-implant children appeared to lag behind their age-matched normalhearing peers for vowel detection and identification, but not for vowel discrimination. Length of cochlear implant use significantly affected vowel processing at the neurophysiologic level, although not systematically. Copyright © 2013 ISCA.

Southern Salentino has a harmony process, where the stressed mid vowels // are raised to mid-high vowels /e, o/ when followed by -i or -u. We studied this process by combining acoustic analyses with ultrasound tongue imaging. The main result of our study is that the Southern Salentino harmonic adjustments in height, which are acoustically manifested in the differentiation of F1, are articulatorily correlated with tongue root advancement when the process is triggered by -i and with tongue body raising when the process is triggered by -u. We propose a phonological analysis of the process based on these findings.