Functional verification of analog devices has become a crucial step in validating mixed-signal SoCs. Waiting for the completion of the analog transistor level can delay time-to-market, as digital verification engineers need to ensure both analog and digital systems function correctly when integrated. Given the availability of efficient, reusable, and reliable digital functional verification methodologies — such as Constrained Random Verification (CRV), functional coverage, assertions/checkers, and Universal Verification Methodology (UVM) — this paper explores how these approaches can be applied to an analog-modeled Device Under Test (DUT) to guarantee its functional correctness. The DUT in question is an Analog Phase-Locked Loop (APLL), a vital component in any Integrated Circuit (IC) system. Its complexity, due to its feedback and closed-loop nature, makes it an ideal example for demonstrating functional verification on a modeled analog DUT. • The digital environment that uses event-driven simulators has a variety of verification techniques and methodologies that are not provided by spice simulators. So, the paper demonstrates enhanced functional verification models for analog device (PLL), which are crucial for validating mixed-signal SoCs because a delaying time-to-market can occur if we wait for the completion of the analog transistor level. Therefore, digital verification engineers need to ensure that both analog and digital systems function correctly when integrated, even before finishing the schematic or gate level. • The paper provides comprehensive tutorials on integrated circuits, which can be highly beneficial to the industry through the methodologies presented in the paper since the Functional verification of analog devices has become a crucial step in validating mixed-signal SoCs. • The paper ensured a comprehensive functional verification methodologies — such as Constrained Random Verification (CRV), functional coverage, assertions/checkers, and Universal Verification Methodology (UVM) — this paper explores how these approaches can be applied to an analog-modeled Device Under Test (DUT) to guarantee its functional correctness. • The DUT in question is an Analog Phase-Locked Loop (APLL), a vital component in any Integrated Circuit (IC) system. Its complexity, due to its feedback and closed-loop nature, makes it an ideal example for demonstrating functional verification on a modeled analog DUT.

Current mode logic (CML) circuits are widely used in digital, analog, and analog/mixed circuits due to their high-speed operation which makes them suitable for RF applications [1] and wireline transceivers [2]. CML amplifier shown in Fig. 1(a) has an output common-mode $(\mathrm{V}_{oCM})$ of where VDD is the supply voltage, I is the bias current and R is the load resistance. Supply voltage and load resistance in (1) are sensitive to PVT variations causing the common-mode voltage to change which may cause the preceding blocks to fail if they do not have a wide input common-mode range. One of the techniques to control the common mode is to apply current trimming by using multiple current mirrors, but this technique suffers from discrete control of each chip during testing. Another approach is to use a poly current reference generator [3] but this approach will require an extra block – reference generator – to be added as in [4] which uses not only a bandgap reference but also an adjust network to select the suitable bias for the CML blocks. Also in [5] instead of using any of the mentioned techniques, a CML to CMOS circuit is used to avoid the change in the output common mode voltage of the CML, but this circuit adds extra delay and power which can cause problems in some systems as in [1]

This paper presents a systematic design methodology for multi-stage feed-forward op-amps used in the active filters of continuous time $\Sigma\triangle$ ADC. This methodology can provide the specifications of each stage in the op-amp (from 2 stages to 4 stages) based on the required ADC specifications and can provide an estimate of the Signal to Noise Ratio (SNR) taking into consideration the effect of the transfer function of the opamp. This method is then validated on a Lowpass and Bandpass $\Sigma\triangle$ ADCs.

Dynamic power is a major source of power dissipation for high speed designs. Domain isolation methodology is a recently-proposed technique for reducing dynamic power based on controlling the evaluation phase of dynamic logic (toggling control). This work demonstrates some design issues in the domain isolation methodology and explains why it is inefficient with pipelined systems. We propose fixes for its identified issues, which enables using the toggling control with pipelined systems in a more efficient way. A novel flow named “Power Reduction Flow” is proposed for reducing dynamic power of digital circuits. Our flow uses novel design analytical methods, novel “Dynamic Logic Modifier Flow”, and novel “Dynmic Logic Area Validation Flow” for reducing dynamic power with conditionally improving performance. The new design analytical methods are based on probability theory, SystemVerilog covergroups, and digital circuit modeling. A new event type perspective is also proposed to analyze designs to reduce dynamic power in them. Experimental results using TSMC 65 nm and low supply voltages show up to 59% power reduction compared to the original traditional techniques with improving circuit's performance by 3× of its original maximum operating frequency at the cost of an extra 12.3% increase in area.

In this paper, a modified assisted opamp technique is proposed for power saving. The original assisted opamp technique adds assistance circuitry to an integrator that results in significant linearity enhancement. The original method utilizes an analog Gm block and a DAC to provide the assistance needed. The proposed method modifies the assistance circuitry implementation, replacing the Gm block with a digital filter. Transistor level simulations for the first integrator in a continuous-time sigma-delta modulator are used to validate and compare the operation of the proposed technique with the original technique in a 180nm CMOS process. The design example uses a 3rdorder 3bit CIFF modulator with a RZ DAC clocked at 100MHz with an OSR of 32.

In this paper we present an adaptive meshing technique suitable for steady state finite element (FE) based thermal analysis of integrated circuits (ICs). The algorithm presented is a non iterative one where the technology used is first pre-characterized. The characterization results are then used for scanning the layout to detect high power regions then fine meshing them. Finally, the analysis is done only once. This makes it faster than conventional iterative adaptive meshing methods. The algorithm results showed comparable accuracy and better performance when compared to the flux based (iterative) and the power aware (non iterative) algorithms.

In this paper, we show that using the relation between the inductance matrix and the capacitance matrix in a homogeneous medium to extract the coupling capacitance in a through silicon via (TSV) array is inaccurate. This is because this relation assumes a lossless, homogeneous surrounding medium. We show that this model can cause an error up to 70% in coupling capacitance compared to Q3D extractor simulations. Instead of using high accuracy, time consuming numerical electromagnetic techniques, we suggest a correction methodology for the inverse inductance model so that it can account for the non-homogeneous nature of the TSVs surrounding medium and the lossy nature of the silicon substrate. Dimensional analysis is used to understand the correction function dependencies on TSV dimensions and to reduce the number of independent variables needed for regression analysis. Once the independent variables are reduced, multiple regression techniques are used to estimate the correction function for TSV arrays. Q3D extractor simulations are used to show that the corrected model reduces the coupling capacitance error significantly. Then, the correction function behavior vs. frequency is discussed.

As VLSI technology pushes into advanced nodes, designers and foundries have exposed a hitherto insignificant set of yield problems. To combat yield failures, the semiconductor industry has deployed new tools and methodologies commonly referred to as design for manufacturing (DFM). Most of the early DFM efforts concentrated on catastrophic failures, or physical DFM problems. Recently, there has been an increased emphasis on parametric yield issues, referred to as electrical-DFM (e-DFM). In this paper, we present a complete e-DFM solution that detects, analyzes, and fixes electrical hotspots (e-hotspots) within an analog circuit design that are caused by different process variations. Novel algorithms are proposed to implement the engines used to develop this solution. The solution is examined on a 130-nm parametrically-failing level shifter circuit, and verified with silicon wafer measurements that confirm the existence of parametric yield issues in the design. Additional experiments are applied on a 65-nm industrial operational amplifier and voltage control oscillator (VCO). E-hotspot devices with a 27.7% variation in dc current are identified. After fixing the e-hotspots, the dc current variation in these devices is dramatically reduced to 7%, which meets the designer acceptance criteria, while saving the original VCO specifications.

A foreground digital calibration technique for pipelined ADC is proposed which accounts for linear error correction, while an error estimation technique for amplifier non-linearity is suggested as a reference for non-linear error correction. The calibration algorithm is based on applying a slow input to the ADC to automatically correct for linear errors, while depending on the accuracy of Digital Error Correction (DEC) to estimate and correct for non-linear errors. The proposed calibration scheme is demonstrated for an 11 bit pipelined ADC, and gives SNDR improvement over 30 dB, while using low specifications residue amplifier to reduce power consumption.

This paper presents a 4-31 programmable frequency divider with dynamic control word built in 90 nm CMOS. The divider uses a chain of 2/3 dual modulus pre-scalar cells. This paper presents a modification to the conventional 2/3 dual modulus pre-scalar building cell. This modification allows changing the control word dynamically during the operation. The divider consists of a chain of four 2/3 dual modulus cells. The maximum operating frequency is 7.9 GHz consuming 24.5 mA at a low voltage supply of 1V.

This paper presents a 1.0-V 13-bit 205-MSample/s double-sampled pipelined analog-to-digital converter (ADC) with a 95-dB spurious free dynamic range (SFDR), a 75.5-dB signal-to-noise-plus-distortion ratio (SNDR) over the full Nyquist band and a total power consumption of 71 mW. This performance is enabled by digital background calibration of both capacitor mismatch in the multi-bit DAC and finite inter-stage gain errors. M-sequence characteristics was used for the generation of the multiple orthogonal codes needed in the calibration engine. Also, a simple design for the dithered re-quantizer which precedes calibration is adopted. Digital calibration achieves an improvement of better than 23-dB in SFDR and 13-dB in SNDR.

A 1-V, high speed, low leakage CML multiplexer suitable for deep submicron technologies, 90 nm and below, is proposed. The CML multiplexer can be used to multiplex high frequency oscillator signals and provide enough isolation to prevent any noticeable signal feed through that might reduce the purity of the multiplexed signals.

Presented in this paper is a tool that automatically migrates analog designs from one process to another while keeping circuit and layout topologies. A netlist migration engine recalculates the new device dimensions in the target technology followed by a layout migration engine that compacts the design according to the new process design rules. The overall framework preserves design intelligence embedded in the original IP such as symmetry, hierarchy, placement and routing. The circuit migration engine, being very fast, can retarget large analog blocks in only a few minutes while giving same or better performance of the original design. The migration of 3 different circuits is presented to validate the overall methodology. These circuits have been fabricated and measured.

In this paper, a simulation-based synthesis tool, AMIGO, for analog cell sizing, is presented. AMIGO is based upon genetic optimization techniques adapted to circuit sizing. A framework has been developed using the TCL/TK language that allows the designer to set the optimization problem, define complex constraint functions, watch the progress of optimization, and finally view the results. To increase design reliability, a sizing-rule pre-processor is incorporated in the tool to automatically generate topology related constraints specific to analog building blocks. Different approaches of using circuit optimizers are demonstrated through the synthesis of three different analog cells: a latched-type comparator, a folded cascode opamp and a switched-capacitor integrator. AMIGO showed to be a successful synthesis tool that can be part of a more general synthesis/migration flow.

The key performance of many analog circuits is directly related to accurate capacitor ratios. It is well known that capacitor ratio precision is greatly enhanced by paralleling identical size unit capacitors in a common-centroid geometry. In this paper, a general algorithm for fitting arbitrary capacitor ratios in a common-centroid unit-capacitor array is presented. The algorithm gives special care to both non-integer and identical ratios in order to minimize mismatch. A method for capacitance mismatch estimation based up-on an oxide gradient model is also introduced. It enables the comparison of different unit-capacitor array assignments. Layout issues are discussed with emphasis on a generic routing model. Both the algorithm and the mismatch estimation method are implemented in an automatic capacitor array generation tool.

This paper presents the complete design methodology of a very low-voltage /spl Delta//spl Sigma/ third-order modulator from high-level specifications down to layout. Behavioral models taking into account cell nonidealities are developed and used to map performance specifications to lower levels. Emphasis has been made on eventual design reuse through design plans and layout templates in a layout-oriented circuit design approach. The modulator has been designed for two different technologies demonstrating the suitability of the methodology for very high performance mixed-signal circuits. Moreover the same design knowledge has been successfully reused in another fourth-order modulator.

This paper presents a methodology for the synthesis of high performance analog circuits. Layout parasitics are estimated and compensated during circuit sizing. Physical layout constraints are thus taken into consideration early in the design. This approach shortens the overall design time by avoiding laborious sizing-layout iterations. The approach has been implemented using two knowledge-based tools dedicated to analog circuit sizing and layout generation. An example of a high performance OTA is presented to illustrate the effectiveness of the approach.

A fully differential opamp suitable for very-low voltage switched-capacitor circuits in standard CMOS technologies is introduced. The proposed two stage opamp needs a simple low voltage CMFB switched-capacitor circuit only for the second stage. Due to the reduced supply voltage, the CMFB circuit is implemented using boot-strapped switches. Minor modifications allow to use chopper stabilization for flicker noise reduction. Two different compensation schemes are discussed and compared using an example for 1 V operation of the amplifier.

A new statistical method for analog fault simulation is presented. The method takes into account process parameter variations and aims to reduce the number of the computational expensive Monte Carlo simulations often required during analog fault simulation. The technique is illustrated by means of a fifth-order low-pass switched-capacitor filter.