Demo Data from EDBT 2026 / reviewers in the wild / expert
Enrica Filippi
dblp:43/980
· DBLP profile ↗
6ranked-venue papers
2as first author
0since 2021 · last 2004
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 first-authorArtificial intelligence and machine learning · 2 · 1 first-authorComputer networks · 1Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Artificial intelligence
1 paper |
Deep learning architectures and training · 50% Efficient and distributed learning · 50% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Hardware accelerators and domain-specific architectures · 52% Electronic design automation · 48% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Machine learning › Deep learning architectures and training
backpropagation |
0.0 | 1 | 1991 | An Analysis on the Performance of Silicon Implementations of Backpropagation Algorithms for Artificial Neural Networks · IEEE Trans. Computers 1991 |
Machine learning › Efficient and distributed learning
low-precision training |
0.0 | 1 | 1991 | An Analysis on the Performance of Silicon Implementations of Backpropagation Algorithms for Artificial Neural Networks · IEEE Trans. Computers 1991 |
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator |
0.0 | 1 | 1991 | An Analysis on the Performance of Silicon Implementations of Backpropagation Algorithms for Artificial Neural Networks · IEEE Trans. Computers 1991 |
Electronic design automation › system-level design
hardware design reuse |
0.0 | 1 | 1999 | FPGA Design Experiences Using the CSELT VIP (TM) Library · FPGA 1999 |
Methods — techniques the papers use, named apart from their topics
batch learning rule · 0.0backpropagation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2004 | Cross-layer perceptual ARQ for H.264 video streaming over 802.11 wireless networksabstractWe present a new cross-layer ARQ algorithm for video streaming over 802.11 wireless networks. The algorithm combines application-level information about the perceptual and temporal importance of each packet into a single priority value, which drives packet selection at each retransmission opportunity. Hence, only the most perceptually important packets are retransmitted, delivering higher perceptual quality and less bandwidth usage compared to the standard 802.11 MAC-layer ARQ scheme. H.264 video streaming based on the proposed technique has been simulated using ns in a realistic home network scenario, using the standard ARQ technique for all interfering traffic. Results show that the proposed method consistently outperforms the standard MAC-layer 802.11 retransmission scheme, delivering more than 1.5 dB PSNR gains using approximately half of the retransmission bandwidth. Paolo Bucciol, Gabriele Davini, Enrico Masala, Enrica Filippi, Juan Carlos De Martin |
GLOBECOM | 4 |
| 1999 | Fast Hardware-Software Co-simulation Using VHDL ModelsabstractWe describe a technique for hardware-software co-simulation that is almost cycle-accurate, and does nor require the use of interprocess communication for a C language interface for the software components. Software is modeled by using behavioral VHDL constructs, annotated with timing information derived from basic block-level timing estimates. Hardware is also modeled in VHDL, and can be either pre-existing intellectual property or synthesized to RTL from a functional specification. Execution of the VHDL processes modeling software tasks is coordinated by a process emulating the target RTOS behavior. The effects of changing the hardware/software partition can be quickly estimated by changing a process parameter defining its target implementation and the processor on which it is running. Bassam Tabbara, Marco Sgroi, Alberto L. Sangiovanni-Vincentelli, Enrica Filippi, Luciano Lavagno |
DATE | 4 |
| 1999 | FPGA Design Experiences Using the CSELT VIP (TM) LibraryabstractNo abstract available. Enrica Filippi, Archille Montanaro, Maurizio Paolini, Maura Turolla |
FPGA | 1 |
| 1994 | Combining multi-layer perceptrons in classification problems
Enrica Filippi, Mario Costa, Eros Pasero |
ESANN | 1 |
| 1994 | A hardware implementation of a biological neural system for target localizationabstractThe optical axes in an array of photoreceptors in the eyes of mantis shrimps have a particular skewing pattern that provides the animal with a monocular distance evaluation. A hardware (HW) device for target recognition was built based on the mathematical model of the biological visual system. The pattern of inputs was simulated by an array of glass fibers connected to phototransistors. In the biological system inputs are picked up by an integrating nerve fiber, in the HW model by an RC network with compartmental threshold devices. The network state is read by a host PC through an array of threshold comparators. The output consists of pulse patterns that can be generated either by a simulation program or in the HW itself. The system can be used as a selective distance/motion detector and can be employed in several applications involving target detection or obstacle avoidance. H. Schiff, P. C. Boarino, Dante Del Corso, Enrica Filippi |
IEEE Trans. Neural Networks | 4 |
| 1991 | An Analysis on the Performance of Silicon Implementations of Backpropagation Algorithms for Artificial Neural NetworksabstractThe effects of silicon implementation on the backpropagation learning rule in artificial neural systems are examined. The effects on learning performance of limited weight resolution, range limitations, and the steepness of the activation function are considered. A minimum resolution of about 20/22 bits is generally required, but this figure can be reduced to about 14/15 bits by properly choosing the learning parameter eta which attains good performance in presence of limited resolution. This performance can be further improved by using a modified batch backpropagation rule. Theoretical analysis is compared with ad-hoc simulations and results are discussed in detail.> Leonardo Maria Reyneri, Enrica Filippi |
IEEE Trans. Computers | 2 |