This paper analyses the phase performance of a RX front-end architecture implemented in a 65-nm CMOS process for linear phased arrays at 24 GHz. The front-end is based on an array of LNAs and phase shifters, which can be used in analog and hybrid beamformers. The penalties of the radiation pattern are associated with metrics calculated from the phase performance. PVT variations and mismatch have been included. Results show that the front-end could potentially attain, in spite of PVT variations, a value near the defined by the mismatch.

The most promising solution for implementing future quantum computers is to merge the operation of the control and readout electronics into the cryogenic environment required by qubits by its monolithic integration using nanometer CMOS processes. To achieve this and follow the integrated circuit design flow, it is mandatory to develop accurate simulation models of the operation of CMOS devices in the deep cryogenic regime. This work provides an analysis of the operation of CMOS integrated polysilicon resistors in conditions of large current density, this is, close to their breakdown voltage. The experimental results show that while current increases in the integrated resistors as temperature is brought to the cryogenic regime, the impact of resistor breakdown is drastically reduced and even eliminated at deep cryogenic temperatures. This will allow for further scaling of these devices when used in quantum computing applications.

This paper presents the design of a differential quadrature all-pass filter as a quadrature generator for being used in a phase shifter operating at 19.5 GHz, employing 65 nm CMOS technology. Various solutions have been investigated to address errors occurring in the phase and magnitude of I/Q signals at the output of the quadrature all-pass filter when connected to the next stage. The best result is obtained when combining asymmetry of the network with the inclusion of two additional resistive elements, achieving a quadrature error lower than$2.0^{\circ}$and a magnitude error lower than of 0.17 from 17 GHz to 22 GHz at the output of the quadrature all-pass filter. As an application, it has been proven that the RMS phase error at the output of a 5-bit active phase shifter has been decreased from$7.6^{\circ}$to$2.3^{\circ}$.

In this paper the potential of CMOS technology will be applied to the design of a new programmable gain amplifier (PGA), for its use in a phase shifter for an array antenna receiver operating over the 18-27 GHz frequency range. The main blocks that will provide the required phase shift are a quadrature signal generator (QSG) followed by a programable gain amplifier (PGA). In addition, the next stage to the phase shifter, consisting of a power combiner, will be added to the design to achieve a better reproduction of the output signal behavior. The PGA topology uses dummy transistors to keep constant the input and output impedances. The phase shifter is digitally programmable using a 4-bit word. The root mean square error at 24 GHz is 3.5º for the phase and 0.76 dB for the gain.

This paper presents the design of a new phase shifter using 65 nm CMOS technology, for its use in a receiver array of antennas operating at the K band (24 GHz). The desired phase shift is obtained by the operation of two main blocks: a quadrature all-pass filter (QAF) and a voltage gain amplifier (VGA). This topology uses dummy transistors to keep constant the input and output impedances. The phase shifter is digitally programmable using a 4-bit word. The root mean square error at 24 GHz is 3.55º for the phase and 0.78 dB for the gain.

In some encryption systems it is necessary to preserve the format and length of the encrypted data. This kind of encryption is called FPE (Format Preserving Encryption) or DPE (Datatype Preserving Encryption). For example, in the case of PCS (Physical Coding Sublayer) at Gigabit Ethernet optical communications, the 8b10b symbol flow can be encrypted at line rate thanks to a symmetric encryption scheme that must preserve the format and coding properties of 8b10b symbols. In this case, since a high speed data flow needs to be encrypted preserving its format, the usage of an FPE stream cipher could be advantageous. For this purpose, a new keystream generator scheme is proposed in this work. It is based on a secure block cipher working in CTR (Counter) mode whose output is subjected to a modulo operation. Moreover, a security analysis for this mode is carried out, deriving an expression for the IND-CPA (Indistinguishability under Chosen Plaintext Attack) advantage of any adversary, concluding that this mode can be considered secure in the same way as traditional modes are. Furthermore, the proposed structure has been implemented over an FPGA (Field Programmable Gate Array) device and adapted to a Gigabit Ethernet application.

This paper presents a didactic strategy based on information and communication technologies (ICTs) to help students build knowledge mental models in the context of Higher Education. It presents a methodology that combines the flipped classroom with other active methodologies and traditional lessons to improve the teaching/learning process of Electronics in university studies in Physics. Using the flipped classroom as the main strategy, the proposed methodology allows devoting more classroom time to active learning so that the instructor can follow the student learning process and evaluate model construction, while at the same time it increases student implication and fosters autonomy and cooperation with peers, contributing to a better construction of knowledge mental models in Electronics.

In this work a new self-synchronized encryption method for 10 Gigabit optical links is proposed and developed. Necessary modifications to introduce this kind of encryption in physical layers based on 64b/66b encoding, such as 10 GBase-R, have been considered. The proposed scheme encrypts directly the 64b/66b blocks by using a symmetric stream cipher based on an FPE (Format Preserving Encryption) block cipher operating in PSCFB (Pipelined Statistical Cipher Feedback) mode. One of the main novelties in this paper is the security analysis done for this mode. For the first time, an expression for the IND-CPA (Indistinguishability under Chosen-Plaintext Attack) advantage of any adversary over this scheme has been derived. Moreover, it has been concluded that this mode can be considered secure in the same way of traditional modes are. In addition, the overall system has been simulated and implemented in an FPGA (Field Programmable Gate Array). An encrypted optical link has been tested with Ethernet data frames, concluding that it is possible to cipher traffic at this level, getting maximum throughput and hiding traffic pattern from passive eavesdroppers.

Information and communication technologies (ICTs) are a privileged instrument to promote and facilitate meaningful student learning. The use of multi-media resources and virtual learning environments has already been adopted in many higher education institutions as part of a mixed learning process. Another tool available for teaching innovation is augmented reality (AR), which allows a combination of digital and physical information in real time using different technological devices. Within the augmented reality, we can find several levels, which start with the 2D codes (QR codes). This work proposes the generation of a set of multi-media resources, accessible by means of QR codes, for the practical sessions in a laboratory of Electronics. With these resources, additional and contextual information is offered, which can be accessed when the student requires it, thus improving the experimental learning process.

A new technique for improving the security of a chaotic cryptosystem has been proposed. An encryption system based on a Skew Tent Map using this technique has been implemented on a Virtex 7 FPGA. The results show that, using this method, the randomness of the sequences can be considerably improved by using a small number of extra resources.

Passive Polyphase Filters (PPF) are extensively used in analog signal processing system which work with quadrature signals, either filtering or generating it. However, the quality of PPF performance in these kinds of operation rely on a perfect matching in components and a symmetrical topology. Thus, mismatch effects could produce notable degradation in PPF response. Despite this, mismatch impact in PPF has not been thoroughly analyzed previously in literature to the best of authors knowledge. In this work, a systematic method is proposed to search the worst possible mismatch in a PPF with any number of stages for a certain tolerance. Then, for the 1-stage case, both PPF types (I and II) are analyzed to evaluate how this non-ideality alters the response of this kind of filters.

In this work a new physical layer encryption method for Ethernet 1000Base-X standard is proposed. The proposed encryption scheme uses a chaotic stream cipher to encrypt the 8b10b symbols flow at PCS (Physical Coding Sublayer) level. The complete system has been implemented in an FPGA (Field Programmable Gate Array). Experimental results are analyzed, concluding that it is possible to cipher traffic at this level and hide the complete Ethernet traffic pattern from any malicious observer. Moreover, no overhead is introduced during encryption and no throughput losses are produced.

A highly-linear low-noise transimpedance amplifier (TIA) with programmable gain for intermediate frequency-over-fiber (IFoF) communications is presented in this paper. It has been fabricated in a 65-nm RF CMOS technology for use in the downlink receiver of remote antenna units for a cost-effective distributed antenna system. The topology consists of a shunt-shunt feedback TIA with open-loop gain control to ensure constant bandwidth, while the transimpedance can be linear-in-dB programmed from 60 to 76 dBO. The IFoF transmission is achieved with a very low error vector magnitude below 2% over an input dynamic range from -16 dBm up to +4 dBm optical power. The TIA shows an equivalent input noise of 8 pA/√Hz at 500 MHz with a bandwidth of 700 MHz. The TIA presents a power consumption of 6 mW from a single supply voltage of 1.2 V, while the total power consumption including the output driver is 19 mW.

In this paper we propose a fast and secure encryption system with a mixed-architecture based on a Modified Logistic Map and a Linear Feedback Shift Register. The system has been simulated showing that it can encrypt and decrypt images efficiently. The encrypted messages have been able to pass the NIST as well as the diehard battery of tests proving that the system is secure.

In this paper, we present a new CMOS analog continuous-time linear equalizer. The proposed structure overcomes some of the limitations due to the low supply voltage of the most widely used continuous-time equalizer, the degenerated differential pair. The prototype has been tested for multi-gigabit short-range applications targeting up to 2 Gb/s through a 50-m SI-POF. The proposed linear equalizer was designed in a cost-effective 90-nm CMOS process. The system is fed with a single supply voltage of 1 V and consumes 2.7 mW.

This paper presents an LC-tank-based voltage-controlled oscillator, fabricated in a standard 0.18 μm CMOS technology, with a 44 % tuning range around a center frequency of 1.7 GHz. To minimize the impact of the proposed oscillator on phase noise in phase-locked-loops, it has a coarse control of 27-1 levels, driven by a 7-bit digital word, achieving a tuning sensitivity below 35 MHz/V along the whole tuning range. The oscillator has -123.4 dBc/Hz phase noise at 1 MHz offset and draws 10 mA from a 1.8 V supply, yielding a total power/tuning/frequency-normalized figure of merit equal to -5.5 dB.

This paper presents a low-voltage CMOS continuous-time adaptive equalizer for short-haul gigabit optical communications. It was designed to compensate the attenuation of a 1.25 Gb/s signal with a simple NRZ modulation, transmitted through a 50-m length 1-mm core step-index plastic optical fiber (SI-POF). The structure includes two adaptation loops to compensate the possible variations in level and spectrum of the input signal. The proposed system was designed in a cost-effective 0.18-µm CMOS process. The system is fed with 1 V and has a total power consumption of 29.3 mW.

This paper presents an optical receiver for short reach applications through low-cost plastic optical fiber. The limited bandwidth caused by the fiber and the external photodiode is compensated by a new adaptive equalizer based on the spectrum balancing technique. A clock and data recovery circuit is included that minimizes jitter and metastability using a new multi-level bang-bang architecture. The prototype, implemented in a standard 0.18-μm CMOS process, achieves 1.25 Gb/s with a power under 110 mW at only 1 V.

The operation of bang-bang phase detectors (BBPDs) in clock and data recovery circuits (CDRs) is typically modeled in terms of the phase difference between their inputs; however, this approach is not sufficient to describe their dynamic behavior completely. This paper introduces a more comprehensive model of the operation of BBPDs that takes into account phase as well as frequency differences between their inputs. Numerical simulations of the operation of a CDR have been carried out to evaluate the validity of the model.

In this paper, a 3.125 GHz four stage voltage controlled ring oscillator is presented. The oscillator has been designed in a 0.18 μm CMOS process with a 1.8 V supply. Behavioural simulations predict an 18% tuning range for the oscillator, with a -91 dBc/Hz phase noise at a 1 MHz offset. Its power consumption has been simulated to be only 12.6 mW.