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Guochong Sui

dblp:430/3235 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2026
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Performance modeling and evaluation · 87% GPUs and heterogeneous computing · 13%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Performance modeling and evaluation › processor performance modeling
accelerator performance modeling
1.012026
CloserToMe: A Unified Framework for Accurate and Transferable Latency Prediction Across Heterogeneous Devices · AAAI 2026
Performance modeling and evaluation › performance prediction
latency prediction
1.012026
CloserToMe: A Unified Framework for Accurate and Transferable Latency Prediction Across Heterogeneous Devices · AAAI 2026

Methods — techniques the papers use, named apart from their topics

hardware-operation interaction modeling · 1.0device behavior profiling · 1.0capability vectors · 1.0
YearPublicationVenuePosition
2026 CloserToMe: A Unified Framework for Accurate and Transferable Latency Prediction Across Heterogeneous Devices
abstract
Hardware accelerators such as GPUs, NPUs, and FPGAs are essential to meeting AI’s computational demands. With the proliferation of heterogeneous devices across cloud and edge, various model optimization techniques adapt to diverse hardware characteristics through operator transformations and structural modifications. Accurate, efficient latency prediction enables rapid selection of optimal strategies across hardware backends. Many existing methods treat hardware as a black-box executor, directly regressing latency without explicitly modeling the intricate interactions between neural network (NN) structures and device-specific execution behaviors. To address these challenges, we introduce a new modeling perspective that captures the interaction between neural architectures and hardware execution. To capture device-specific characteristics, we propose two complementary modeling strategies. The Device Behavior Signature Selector (DBSel) characterizes hardware execution behavior by selectively probing a small set of representative architectures, forming a compact, workload-driven profile. In parallel, we construct capability vectors that capture the hierarchical memory of each device and compute characteristics, providing a structured abstraction of its architectural capacity. To unify both behavioral and structural views, we introduce the Hardware–Operation Dialogue Module (HODM), which models fine-grained interactions between neural operators and hardware properties. Together, these components empower CloserToMe to deliver accurate and transferable latency predictions across unseen and diverse platforms.
Cheng Tang 0004, Guochong Sui, Wenqi Lou, Jiayi Tuo, Wenqian Xie, Yinkang Gao, Yixuan Zhu, Lei Gong 0003, Chao Wang 0003, Xuehai Zhou
AAAI2