Demo Data from EDBT 2026 / reviewers in the wild / expert
Byungyo Lee
dblp:430/7371
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2026
0009-0005-4790-436XORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 88% Cloud and datacenter computing · 12% | |
| Databases, data mining, and information retrieval
1 paper |
Information retrieval · 100% |
Topics — the 4 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Information retrieval
retrieval-augmented generation |
1.0 | 1 | 2026 | Performance Analysis and CXL Memory Optimization in Cluster-Based RAG Systems · IEEE Trans. Computers 2026 |
Memory systems › memory disaggregation
CXL memory |
1.0 | 1 | 2026 | Performance Analysis and CXL Memory Optimization in Cluster-Based RAG Systems · IEEE Trans. Computers 2026 |
Memory systems
tiered memory |
1.0 | 1 | 2026 | Performance Analysis and CXL Memory Optimization in Cluster-Based RAG Systems · IEEE Trans. Computers 2026 |
Cloud and datacenter computing › cluster resource management and scheduling
cluster resource management |
0.3 | 1 | 2026 | Performance Analysis and CXL Memory Optimization in Cluster-Based RAG Systems · IEEE Trans. Computers 2026 |
Methods — techniques the papers use, named apart from their topics
weighted interleaving · 2.0memory tiering · 2.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Performance Analysis and CXL Memory Optimization in Cluster-Based RAG SystemsabstractRetrieval-augmented generation (RAG) systems rely on large-scale embedding search. However, the growth of corpora and the demand for real-time queries expose the memory capacity and bandwidth limitations of DRAM-centric architectures. To address this challenge, we adopt CXL memory in conjunction with cluster-scale RAG deployments and optimize the system in terms of performance, latency and cost efficiency. Our design leverages state-of-the-art CXL memory devices and platforms with memory management policies such as weighted interleaving and tiering between DRAM and CXL memory. In comparison with a DRAM baseline, our system archives 20% higher vector search performance and 43% lower LLM time-to-first token (TTFT), demonstrating clear end-to-end performance benefits. Moreover, in the context of overall system efficiency, we observed up to 20% and 42% improvement in power efficiency (QPS/Watt) and cost efficiency (QPS/$), respectively. These results demonstrate that, despite the relatively high latency of CXL memory, memory management policy-level optimization enable CXL memory to serve as a first-class memory resource in cluster-based RAG systems. Jesin Kim, Hochul Shin, Byeonghun Hwang, Seungpyo Cho, Kyumin Park, Young Geon Yoo, Byungyo Lee, Hojun Shim |
IEEE Trans. Computers | 7 |