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Hong-Ruei Lin

dblp:431/1642 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2026
0009-0002-2227-2966ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Storage systems · 38% Hardware accelerators and domain-specific architectures · 38% Hardware reliability and fault tolerance · 24%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › machine learning accelerator › DNN inference
CNN inference
1.012026
Graceful CNN Model Degradation in Uncorrected Flash Storage for Embedded Edge Devices · ACM Trans. Storage 2026
Hardware accelerators and domain-specific architectures
edge intelligence
1.012026
Graceful CNN Model Degradation in Uncorrected Flash Storage for Embedded Edge Devices · ACM Trans. Storage 2026
Hardware reliability and fault tolerance
error protection
1.012026
Graceful CNN Model Degradation in Uncorrected Flash Storage for Embedded Edge Devices · ACM Trans. Storage 2026
Storage systems
flash and SSD
1.012026
Graceful CNN Model Degradation in Uncorrected Flash Storage for Embedded Edge Devices · ACM Trans. Storage 2026
Storage systems › storage reliability › durability
retention failure
1.012026
Graceful CNN Model Degradation in Uncorrected Flash Storage for Embedded Edge Devices · ACM Trans. Storage 2026
Hardware reliability and fault tolerance
soft errors
0.312026
Graceful CNN Model Degradation in Uncorrected Flash Storage for Embedded Edge Devices · ACM Trans. Storage 2026

Methods — techniques the papers use, named apart from their topics

bit pattern mapping · 1.0adaptive cell-bit density · 1.0
YearPublicationVenuePosition
2026 Graceful CNN Model Degradation in Uncorrected Flash Storage for Embedded Edge Devices
abstract
Computing near the source of data has been proven effective in terms of energy conservation, latency improvement, and privacy preservation. With this, edge intelligence refers to local CNN inference in embedded edge devices. Because edge devices are highly resource-constrained, in practice they store CNN model(s) in external flash memory and load them (or part of) during runtime inference. However, flash memory is subject to time-related retention errors, and thus a dilemma is that without error correction, a CNN model in flash memory quickly deteriorates and becomes useless. On the other hand, strong error correction involves extra read sensing and read retrying. Due to the concern of reliability, the lineup of embedded serial flash memory offers low-density solutions only. In this study, we investigate graceful degradation of CNN models in uncorrected high-density flash storage for edge intelligence. Inspired by the observation that in popular CNN models, the majority of CNN weight parameters share a few monotonic bit patterns in their high-order bits, we propose mapping the frequent bit patterns to low flash-cell voltage levels for protection against retention errors. Furthermore, as CNN layers show different levels of tolerance to bit errors, we also propose using adaptive cell-bit density to provide non-uniform error protection among layers. We conducted experiments on popular CNN designs, including VGG16, ResNet50, and InceptionV3, under realistic effects of flash aging. Results show that with prior methods, the inference accuracy of ResNet50 degrades to 70.7% in just three months; by contrast, with our approach, the degradation is less than 1% and the accuracy remains at 91.6% after one year of retention.
Hung-Yi Chen, Jin-Wei Chang, Hong-Ruei Lin, Li-Pin Chang
ACM Trans. Storage3