Demo Data from EDBT 2026 / reviewers in the wild / expert
Kunshi Wang
dblp:431/5442
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2026
0009-0008-9683-1138ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 61% Integrated circuit design · 30% Hardware accelerators and domain-specific architectures · 9% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
analog and mixed-signal circuits |
1.0 | 1 | 2026 | EvaCAM: A Circuit-Level Evaluation Tool for General Content Addressable Memories · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026 |
Memory systems
content-addressable memory |
1.0 | 1 | 2026 | EvaCAM: A Circuit-Level Evaluation Tool for General Content Addressable Memories · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026 |
Memory systems
processing-in-memory |
1.0 | 1 | 2026 | EvaCAM: A Circuit-Level Evaluation Tool for General Content Addressable Memories · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026 |
Hardware accelerators and domain-specific architectures › machine learning accelerator
in-memory computing accelerator |
0.3 | 1 | 2026 | EvaCAM: A Circuit-Level Evaluation Tool for General Content Addressable Memories · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026 |
Methods — techniques the papers use, named apart from their topics
design space exploration · 1.0circuit-level modeling · 1.0SPICE simulation · 1.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | EvaCAM: A Circuit-Level Evaluation Tool for General Content Addressable MemoriesabstractContent addressable memories (CAMs) are special-purpose in-memory computing units that support parallel searches directly in memory. There is growing interest in CAMs for data-intensive applications such as machine learning, data mining, and bioinformatics, which has led to a rapidly growing CAM design space. CAM cells can be implemented exclusively by CMOS or with various non-volatile memory (NVM) devices. In addition to traditional binary and ternary CAMs (BCAMs and TCAMs), analog CAM (ACAM) and multi-bit CAM (MCAM) designs have recently been introduced, which could further improve density, and also support unique in-memory distance functions. Furthermore, aside from the widely-used exact match function, CAM-based approximate match functions, such as threshold match and best match, have been proposed to further extend the utility of CAMs to new application spaces. As the CAM design space is large, evaluating different CAM design options for a given application is both crucial and challenging. This paper presents EvaCAM, a circuit-level modeling and evaluation tool for CAMs. EvaCAM supports TCAM, ACAM, and MCAM designs implemented in either CMOS or NVMs, for both exact and approximate match functions. It also allows for the exploration of different CAM designs under various optimization targets. EvaCAM has been validated against measured data from fabricated chips and detailed SPICE simulations. A comprehensive design space exploration for CAMs is provided to illustrate the impact of various design decisions and to demonstrate the use cases of EvaCAM. Liu Liu 0023, Mohammad Mehdi Sharifi, Kunshi Wang, Ruibin Mao, Kai Ni 0004, Can Li 0024, Xunzhao Yin, Michael T. Niemier, Xiaobo Sharon Hu |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |