Process-in-memory (PIM) accelerators demonstrate outstanding performance in accelerating matrix-vector multiplication (MVM) tasks in neural networks. To achieve better acceleration performance, extensive research has focused on the design of hierarchical tile-based PIM architectures, presenting challenges for the hardware deployment of algorithms. Multilayer parallelism in tile-based architectures requires the support of dataflow optimization techniques. However, existing research primarily performs dataflow analysis using computational models and performance metrics that are not suitable for tile-level dataflows. In this paper, we propose an analytical framework, PIMapping, for tile-based PIM architectures that supports multi-layer parallelism mapping and tile-level dataflow optimization. In this work, we first establish a general dataflow representation for tile-level dataflow, which serves as an intermediate representation (IR) for multi-layer DNN mapping and scheduling tasks at tile level. Next, based on the proposed representation, we introduce a data proximity-based mapping method aimed at minimizing the inter-tile communication overhead. Furthermore, we propose a congestion-aware scheduling algorithm to minimize inter-tile communication conflicts. Experimental case-studies are conducted to map common DNN algorithms onto different PIM architectures. The results demonstrate significant improvements over the state-of-the-art mapping framework in terms of communication latency, required inter-tile bandwidth, and pipeline efficiency.