With the advancement of computing systems, the demand for energy-efficient NVMs has increased due to the recent challenges of traditional memory technologies like SRAMs and DRAMs. Thus, alternative NVMs like STT-MRAM have gained significance. However, one of the significant challenges of STT-MRAMs, is their stochastic/unreliable write operations. To address this, a noticeable amount of energy should be applied to the STT-MRAM cell to perform a reliable write operation. While reliable write operation in STT-MRAMs matter, there are many situations in which the applied write energy is more than enough for the required reliability level. In this research, we proposed VS-ReLEnT to balance the reliability and energy consumption of STT-MRAMs cache write operations. In VS-ReLEnT the write voltage actuation knob of the STT-MRAM-based cache is controlled by a Reinforcement Learning (RL) algorithm. Accordingly, based on the contents that will be written on the STT-MRAM cache block, the suitable voltage is chosen by VS-ReLEnT and applied to the cells. This allows the adjustment of each level of VS-Relent to the most suitable reliability level. The simulation results demonstrate an average energy improvement of 16% compared to the golden case, where all data is written with the highest reliability level while preserving reliability in the system. Conversely, the area overhead and imposed leakage energy of VS-ReLEnT show only a marginal increase of 0.24% and 0.21%, respectively.