Modern digital systems in communication, control, and sensing rely on fast and accurate hardware evaluation of trigonometric functions. The classic CORDIC algorithm provides a multiplier-less solution using iterative shifts and adds, but conventional CORDIC requires many iterations and a final scaling correction that increases latency and hardware cost. Scaling-Free CORDIC (SF-CORDIC) eliminates the scaling factor by adjusting micro-rotation angles to achieve a net gain of unity. However, this approach introduces fixed constant multiplications at each iteration, which can dominate hardware resources and critical path delay. Existing methods often restrict the set of rotation angles so that constants can be implemented with simple add-shift operations. Other approaches use high-radix or hybrid schemes, but these methods limit the angle accuracy, introduce extra complexity, and still rely on numerous add-shift networks. To address these issues, a new SF-CORDIC architecture is proposed to eliminate per-iteration multipliers by using the time-multiplexed constant multiplier units implemented across all iterations. Bit-width growth is controlled via shift propagation and a minor compensation step, maintaining precision without a final scaling stage. This compact, low-latency design significantly reduces hardware area and delay compared to prior SF-CORDIC implementations while preserving high output accuracy. In a six-stage FPGA pipeline, the design reaches a maximum clock frequency of 216.03 MHz with an end-to-end latency of 27.78 ns. It uses about 1200 LUTs and 300 registers. The root-mean-square error is 6.8 × 10−5for sine and 6.4 × 10−5for cosine.