In this paper, we propose a new framework to synthesize rapid single flux quantum (RSFQ) logic circuits. In our framework, we construct a virtual cell, which we call "2-AND/XOR," from the RSFQ logic primitives. By using 2-AND/XOR cells, we can successfully adopt the conventional logic design techniques into our framework, and thus we can successfully generate RSFQ circuits in reasonable time even for large benchmark circuits that have not been reported in the existing researches

This presentation gives a new SPFD-based method to make a target wire redundant with higher possibility than the previous rewiring methods. After placement and routing, we obtain or estimate how much the existing and candidate wires interferes such physical design, and thus, we find out the most critical one of the existing wires. In order to remove it, the previous methods add new input wires to only one LUT. Actually, in the context of gate/cell-based logic optimization, it is well-known that input wire addition to many gates/cells is likely to make the critical one redundant. However, in an FPGA circuit, since an LUT can realize an arbitrary function for a specified number of inputs, such wire addition has never been considered to be useful. In this presentation, we provides with an SPFD-based condition for such wire addition to improve the FPGA circuit performance. We also present several experimental results to show the effectiveness of the proposed condition.

This paper proposes an innovative method for SPFD-based rewiring in Look-Up-Table-based (LUT-based) FPGA circuits. The new method adds new input wires to two or more LUT's in order to remove or to replace a target wire. There have been a few rewiring methods for FPGA circuits so far, such as the original SPFD-based optimization sometimes called Local Rewiring (LR), SPFD-based Global Rewiring (GR) and SPFD-based Enhanced Rewiring (ER). However, all of them replace one wire with other new input wire to one LUT but not with those to two or more LUT's. Moreover, the LR removes or replaces input wires with new one to the same LUT only, and the GR and ER topologically limit the LUT's where new input wires are added. Our new method, called One-to-Many Rewiring (OMR), loosens such topological constraints for more flexible FPGA circuit transformation so that it is easier to import constraints on physical design to the logic optimization. The experimental results show our OMR can transform FPGA circuits more flexibly than the LR, GR and ER, by introducing the new manipulation, wire addition. The OMR can rewire 1.2 times as many wires as the existing methods, especially, the ER. The computation time is as short as the existing methods.