The authors describe a high-level functional analog simulator for hybrid logic/analog networks. it forms one level of an experimental multilevel simulation system which is currently under development. The functional simulator is described in detail, and the structure of the multilevel simulator is briefly outlined. It can be used as a stand-alone system but was developed specifically for coupling with other levels of simulation which also use time responses (or voltage waveforms). Since Boolean algebra cannot operate with time responses, a new algebra is developed. It eliminates the unknown state, the main obstacle in coupling analog simulation to logic simulation. Logic states are replaced by operations on time functions, in this case represented by piecewise linear segments. High-level analog operations are also possible. The simulator based on these ideas was used to solve several high-level analog problems. The examples presented demonstrate its application.>

A switch-level logic simulator for MOS networks based on the theory of current-limited switches is described. It was derived from a switch-level timing simulator by suppressing time-related information and by eliminating invalid events. The simulator obeys Kirchoff's laws and after initialization every node has a known voltage. It can thus be used to drive analog simulation. Fault simulation is easily incorporated by representing the line-open fault by an open circuit and the node-short fault by a short circuit. Examples demonstrate application to both logic and fault simulation.>

An algorithm for switch-level timing simulation of MOS logic networks is proposed. The event-driven simulator, WATSWITCH, partitions the circuit into subblocks which are solved by replacing each transistor by a special current-limited switch. Because of the choice of the switch model, time-domain responses are obtained without model evaluations during the simulation, without table lookup, and without time-domain integration. This is achieved by allowing only capacitors and piecewise-constant current sources to be the elements of the simulator. Because resistors are not allowed, the time responses are known to be piecewise-linear segments. As a consequence, neither numerical integration nor transistor model evaluation is needed during the simulation.>