Many modern embedded systems have end-to-end (EtoE) latency constraints that necessitate precise timing to ensure high reliability and functional correctness. The combination of high-level synthesis (HLS) and design space exploration (DSE) enables the rapid generation of embedded systems using various constraints/directives to find Pareto-optimal configurations. Current HLS DSE approaches often address latency by focusing on individual components, without considering the EtoE latency during the system-level optimization process. However, to truly optimize the system under EtoE latency, we need a holistic approach that analyzes individual system components’ timing constraints in the context of how the different components interact and impact the overall design. This article presents a novel system-level HLS DSE approach, called EtoE-DSE, that accommodates EtoE latency and variable timing constraints for complex multicomponent application-specific embedded systems. EtoE-DSE employs a latency estimation model and a pathfinding algorithm to identify and estimate the EtoE latency for paths between any endpoints. It also uses a frequency-based segmentation process to segment and prune the design space, alongside a latency-constrained optimization algorithm for efficiently and accurately exploring the system-level design space. We evaluate our approach using a real-world use case of an autonomous driving subsystem compared to the state-of-the-art in HLS DSE. We show that our approach yields substantially better-optimization results than prior DSE approaches, improving the quality of results by up to 89.26%, while efficiently identifying Pareto-optimal configurations in terms of energy and area.

High-Level Synthesis (HLS) Design Space Exploration (DSE) is a widely accepted approach for efficiently exploring Pareto-optimal and optimal hardware solutions during the HLS process. Several HLS benchmarks and datasets are available for the research community to evaluate their methodologies. Unfortunately, these resources are limited and may not be sufficient for complex, multi-component system-level explorations. Generating new data using existing HLS benchmarks can be cumbersome, given the expertise and time required to effectively generate data for different HLS designs and directives. As a result, synthetic data has been used in prior work to evaluate system-level HLS DSE. However, the fidelity of the synthetic data to real data is often unclear, leading to uncertainty about the quality of system-level HLS DSE. This paper proposes a novel approach, called Vaegan, that employs generative machine learning to generate synthetic data that is robust enough to support complex system-level HLS DSE experiments that would be unattainable with only the currently available data. We explore and adapt a Variational Autoencoder (VAE) and Generative Adversarial Network (GAN) for this task and evaluate our approach using state-of-the-art datasets and metrics. We compare our approach to prior works and show that Vaegan effectively generates synthetic HLS data that closely mirrors the ground truth’s distribution.

The increasing complexity and demand for faster, energy-efficient hardware designs necessitate innovative High-Level Synthesis (HLS) methodologies. This paper explores the potential of Large Language Models (LLMs) to streamline or replace the HLS process, leveraging their ability to understand natural language specifications and refactor code. We survey the current research and conduct experiments comparing Verilog designs generated by a standard HLS tool (Vitis HLS) with those produced by LLMs translating C code or natural language specifications. Our evaluation focuses on quantifying the impact on performance, power, and resource utilization, providing an assessment of the efficiency of LLM-based approaches. This study aims to illuminate the role of LLMs in HLS, identifying promising directions for optimized hardware design in applications such as AI acceleration, embedded systems, and high-performance computing.

High-level synthesis (HLS) is a rapidly evolving and popular approach to designing, synthesizing, and optimizing embedded systems. Many HLS methodologies utilize design space exploration (DSE) at the post-synthesis stage to find Pareto-optimal hardware implementations for individual components. However, the design space for the system-level Pareto-optimal configurations is orders of magnitude larger than component-level design space, making existing approaches insufficient for system-level DSE. This paper presents Pruned Genetic Design Space Exploration (PG-DSE)---an approach to post-synthesis DSE that involves a pruning method to effectively reduce the system-level design space and an elitist genetic algorithm to accurately find the system-level Pareto-optimal configurations. We evaluate PG-DSE using an autonomous driving application subsystem (ADAS) and three synthetic systems with extremely large design spaces. Experimental results show that PG-DSE can reduce the design space by several orders of magnitude compared to prior work while achieving higher quality results (an average improvement of 58.1x).

Side-channel attacks (SCA) have been studied for several decades, which resulted in many techniques that use statistical models to extract system information from side channels. More recently, machine learning has shown significant promise to advance the ability for SCAs to expose vulnerabilities. Artificial neural networks (ANN) can effectively learn nonlinear relationships between features within a side channel. In this paper, we propose a multi-architecture data aggregation technique to profile power traces for a system with an embedded processor that is based on three types of deep NNs, namely, multi-layer perceptrons (MLP), convolutional neural networks (CNN), and recurrent neural networks (RNN). This is one of the first works to explore the inter-architecture portability of NNs and SCAs. We demonstrate the robustness of the ANNs performing power-based SCAs on multiple architecture configurations with different architectural features, such as L1/L2 caches' size and associativity, and system memory size. We provide a comprehensive set of benchmarks to demonstrate that architecturally identical devices are not essential for profile-based SCAs

College textbook publishing is transforming from a model of static textbooks to a modern model of customizable textbooks. Customization may involve reconfiguring content, combining textbooks, authoring one's own content, adding notes to content, and more. As such, publishing is moving away from a model of selling static textbooks, and toward a model of providing a library of content from which instructors can build a course. This Full Paper provides data for one digital-only publisher, zyBooks, on the prevalence and trends around reconfiguring and combining Computer Science and Engineering textbooks, instructor-authored sections, and instructor-added notes. The data show that for over 4,000 classes in 2020, over 85% of classes reconfigured their books, over 30% of classes combined two or more books with hundreds combining three or more, about 30% of books had instructor notes added, and about 65% of zyLabs-enabled zyBooks included instructor-created labs. The trend away from static textbooks and toward customizable content has substantial implications on how content is authored, requiring more modularity of content sections to support reconfiguration, and requiring more consistency across subjects to enable combining content. The trend also has substantial implications on book marketing, pricing, renewals, and more.

With billions of networked connected embedded systems, the security historically provided by the isolation of embedded systems is no longer sufficient. Millions of new malware are created every month and zero-day attacks are becoming an increasing concern. Therefore, proactive security measures are no longer enough to provide protection to embedded systems. Instead, reactive approaches that detect attacks that can circumvent the proactive defenses and react upon them are needed. Anomaly-based detection is a common reactive approach employed to detect malware by monitoring anomalous deviations in the system execution. Timing-based anomaly detection detects malware by monitoring the system's internal timing, which offers unique protection against mimicry malware compared to sequence-based anomaly detection. However, previous timing-based anomaly detection methods focus on each operation independently at the granularity of tasks, function calls, system calls, or basic blocks. These approaches neither consider the entire software execution path nor provide a quantitative estimate of the presence of malware. This article presents a novel model for specifying the normal timing for execution paths in software applications using cumulative distribution functions of timing data in sliding execution windows. A probabilistic formulation is used to estimate the presence of malware for individual operations and sequences of operations within the paths. Operation and path-based thresholds are determined during the training process to minimize false positives. Finally, the article presents an optimization method to assist system developers in selecting which operations to monitor based on different optimization goals and constraints. Experimental results with a smart connected pacemaker, an unmanned aerial vehicle, and seven sophisticated mimicry malware implemented at different levels demonstrate the effectiveness of the proposed approach.

In this article, we assess the string stability of seven 2018 model yearadaptive cruise control(ACC) equipped vehicles that are widely available in the US market. Seven distinct vehicle models from two different vehicle makes are analyzed using data collected from more than 1,200 miles of driving in car-following experiments with ACC engaged by the follower vehicle. The resulting dataset is used to identify the parameters of a linear second order delay differential equation model that approximates the behavior of the black box ACC systems. The string stability of the data-fitted model associated with each vehicle is assessed, and the main finding is that all seven vehicle models have string unstable ACC systems. For one commonly available vehicle model that offers ACC as a standard feature on all trim levels, we validate the string stability finding with a multi-vehicle homogeneousplatoon experiment in which all vehicles are the same year, make, and model. In this test, an initial disturbance of 6 mph is amplified to a 25 mph disturbance, at which point the last vehicle in the platoon is observed to disengage the ACC. The data collected in the driving experiments is made available, representing the largest publicly available comparative driving dataset on ACC equipped vehicles.

This paper presents BackFlow, a compiler-based toolchain that enforces indirect backward edge control flow integrity for low-end ARM Cortex-M microprocessors. BackFlow is implemented within the Clang/LLVM compiler and supports the ARM instruction set and its subset Thumb. The control flow integrity generated by the compiler relies on a bitmap, where each set bit indicates a valid pointer destination. The efficiency of the framework is benchmarked using an STM32 NUCLEO F446RE microcontroller. The obtained results show that the control flow integrity solution incurs an execution time overhead ranging from 1.5 to 4.5%.

This paper presents a statistical method based on cumulative distribution functions (CDF) to analyze an embedded system's behavior to detect anomalous and malicious executions behaviors. The proposed method analyzes the internal timing of the system by monitoring individual operations and sequences of operations, wherein the timing of operations is decomposed into multiple timing subcomponents. Creating the normal model of the system utilizing the internal timing adds resilience to zero-day attacks, and mimicry malware. The combination of CDF-based statistical analysis and timing subcomponents enable both higher detection rates and lower false positives rates. We demonstrate the effectiveness of the approach and compare to several state-of-theart malware detection methods using two embedded systems benchmarks, namely a network connected pacemaker and an unmanned aerial vehicle, utilizing seven different malware.

This article addresses the challenges of memory safety in life-critical medical devices. Since the last decade, healthcare manufacturers have embraced the Internet of Things, pushing technological innovations to increase market share. Medical devices, including the most critical ones, tend to be increasingly connected to the Internet. Unfortunately, as critical devices often rely on unsafe programming languages such as C, they are no exception to memory safety issues. Given a memory vulnerability, a skillful attacker can take over a system and perform remote code execution. Combined with the fact that medical devices directly impact the safety of their users, a security vulnerability can lead to disastrous scenarios. To address this issue, this article presents TrustFlow-X, a novel hardware/software co-designed framework that provides efficient fine-grained control-flow integrity protection against memory-based attacks. The TrustFlow-X framework is composed of an LLVM-based compiler toolchain that generates a secure code. This secure code is then executed on an extended RISC-V processor that keeps track of sensitive data using a trusted memory. The obtained results show that the contribution is practical, providing a high level of trust in life-critical embedded systems.

Dynamic data-driven applications such as object tracking, surveillance, and other sensing and decision applications are largely dependent on the characteristics of the data streams on which they operate. The underlying models and algorithms of data-driven applications must continually adapt at runtime to changes in data quality and availability to meet both functional and designer-specified performance requirements. Given the dynamic nature of these applications, point solutions produced by traditional design tools cannot be expected to perform adequately across varying execution scenarios. Additionally, the increasing diversity and interdependence of application requirements complicates the design and optimization process. To assist designers of data-driven applications, we present a modeling and optimization framework that enables developers to model an application's data sources, tasks, and exchanged data tokens; specify application requirements through high-level design metrics and fuzzy logic--based optimization rules; and define an estimation framework to automatically optimize the application at runtime. We demonstrate the modeling and optimization process via an example application for video-based vehicle tracking and collision avoidance. We analyze the benefits of runtime optimization by comparing the performance of static point solutions to dynamic solutions over five distinct execution scenarios, showing improvements of up to 74% for dynamic over static configurations. Further, we show the benefits of using fuzzy logic--based rules over traditional weighted functions for the specification and evaluation of competing high-level metrics in optimization.

This innovative practice full paper presents new learning content, developed natively for the web, that teaches core programming concepts using interactive activities, such as animations, learning questions, and interactive tools, in addition to text and figures. The core programming concepts are topics typically covered in CS1 (and often in CS0), including input/output, variables, branching, loops, arrays, and functions. Usually, programming is introduced with an industry language, such as Java or Python, which were developed for professionals, not for students. Sometimes, programming is introduced visually, such as Scratch or Alice, but many instructors want a more serious feel for college students, writing textual code. Our content teaches programming using an ultra-simple language, Coral, designed specifically to teach core concepts. The content presents a Coral program as code or a flowchart that closely resembles the code's structure. Each chapter starts by introducing the programming concept visually with flowchart examples, so students develop a strong ability to read a program and understand how the program executes. Later in the chapter, the content introduces the corresponding textual code. The student then writes code to solve homework problems. Such incremental learning (first master program reading, then master program writing) is a key feature. Another key feature is a strong emphasis on visualization and intuition: The content uses animations that show Coral programs being executed line-by-line, along with variables shown in memory, including variable value updates from assignments. Further, the content has an online educational simulator where a student or instructor can write and execute Coral code. This paper includes early student usage data, such as amount of time spent to complete learning and homework, that shows students can quickly learn programming concepts. Some surveyed students commented on liking the incremental practice.

Edge computing on the Internet of Things (IoT) is an increasingly popular paradigm in which computation is moved closer to the data source (i.e., edge devices). Edge computing mitigates the overheads of cloud-based computing arising from increased response time, communication bandwidth, data security and privacy, energy consumption, etc. However, given the potentially stringent resource constraints and functional requirements of emerging IoT devices, edge computing must neither be over- or under-provisioned for its stated purpose. In this paper, we present an overview of the problem of right-provisioned IoT edge computing, wherein IoT devices are equipped with resources that are 'just enough,' even when 'just enough' may not be clearly defined at design time. We highlight a few research directions and key challenges that must be addressed to enable right-provisioned IoT edge computing.

Runtime monitoring and verification enables a system to monitor itself and ensure system requirements are met even in the presence of dynamic environments. For hardware, state-based models are widely used, but verifying the correctness between the state-based model and hardware implementation is time- consuming and difficult. This paper presents a novel method for extracting hardware verification requirements from state-based hardware models to construct a hierarchical runtime monitoring graph that can be efficiently used at runtime to verify correctness.

Program auto-graders used to be tough applications to install and use by instructors, meaning many instructors avoided them, and for those that used them, most assignments were created by specialists with scripting and other expertise. As such, creating new auto-graded programming assignments was a rare event done by just a few people. But modern cloud-based program auto-graders enable nearly any instructor or TA to create new auto-graded assignments in just tens of minutes, fully created and carried out via the web. This capability has led to an explosion in the number of instructors and TAs creating auto-graded programming assignments, benefiting students via immediate feedback and the option to resubmit, and saving teachers huge amounts of grading time. BUT, this new frontier is very different from hand-graded assignments, with plenty of pitfalls for teachers to avoid, and emerging best practices. This BOF allows teachers to share do's and don'ts, so each can improve their use of auto-graded labs, and teachers new to auto-graded labs can benefit from others' experiences. Special focus is on early CS classes (CS0, CS1, CS2) but topics may apply to many CS classes.

Malware is a serious threat to network-connected embedded systems, as evidenced by the continued and rapid growth of such devices, commonly referred to as the Internet of Things. Their ubiquitous use in critical applications require robust protection to ensure user safety and privacy. That protection must be applied to all system aspects, extending beyond protecting the network and external interfaces. Anomaly detection is one of the last lines of defence against malware, in which data-driven approaches that require the least domain knowledge are popular. However, embedded systems, particularly edge devices, face several challenges in applying data-driven anomaly detection, including unpredictability of malware, limited tolerance to long data collection windows, and limited computing/energy resources. In this article, we utilize subcomponent timing information of software execution, including intrinsic software execution, instruction cache misses, and data cache misses as features, to detect anomalies based on ranges, multi-dimensional Euclidean distance, and classification at runtime. Detection methods based on lumped timing range are also evaluated and compared. We design several hardware detectors implementing these data-driven detection methods, which non-intrusively measuring lumped/subcomponent timing of all system/function calls of the embedded application. We evaluate the area, power, and detection latency of the presented detector designs. Experimental results demonstrate that the subcomponent timing model provides sufficient features to achieve high detection accuracy with low false-positive rates using a one-class support vector machine, considering sophisticated mimicry malware.

This paper presents a methodology for evaluating power obfuscation approaches that seek to obfuscate the location of sensitive operations in the power trace, thereby increasing the complexity of automated trace alignment. The paper presents a new adversary model and proposes a new metric, mean trials to success (MTTS), to evaluate power obfuscation methods in the context of automated trace alignment. We evaluate two common obfuscation methods, namely instruction shuffling and random instruction insertion, and we present a new obfuscation method using power shaping to intentionally mislead the attacker.

With billions of networked connected embedded systems, the security historically provided by the isolation of embedded systems is no longer sufficient. Both proactive security measures that prevent intrusions and reactive measures that detect intrusions are essential. Anomaly-based detection is a common reactive approach employed to detect malware that has evaded proactive defenses by observing anomalous deviations in the system execution. Timing-based anomaly detection detects malware by monitoring the system's internal timing, which offers unique protection against mimicry malware compared to sequence-based anomaly detection. However, previous timing-based anomaly detection methods focus on each operation independently at the granularity of tasks, function calls, system calls, or basic blocks. These approaches neither consider the entire software execution path nor provide a quantitative estimate of the presence of malware. This paper presents a novel model for specifying the normal timing for execution paths in software applications using cumulative distribution functions of timing data in sliding execution windows. We present a probabilistic formulation for estimating the presence of malware for individual operations and sequences of operations within the paths, and we define thresholds to minimize false positives based on training data. Experimental results with a smart connected pacemaker and three sophisticated mimicry malware demonstrate improved performance and accuracy compared to state-of-the-art timing-based malware detection.

With embedded systems and IoT devices being widely deployed nowadays, their security becomes a major concern. Among all possible attacks, side channel attacks (SCA) represent a major source of threats. For power side channels, template attacks have been proven to be efficient and widely applicable. Traditional template attacks require physical access to an identical target device for extensive profiling to construct the attack template. In this paper, we present a composable template attack that relaxes this requirement by constructing the attack template as a composition of templates from individual architectural components, including processor, caches, and memories. The proposed approach enables an attacker to construct a template using only information of a system's components and device models thereof.

Many teachers of CS 1 (introductory programming) have switched to Python rather than C, C++, or Java. One reason is the belief that Python's interpreted nature plus simpler syntax and semantics ease a student's learning, but data supporting that belief is scarce. This paper addresses the question: Do Python learners struggle less than C++ learners? We analyzed student submissions on small coding exercises in CS 1 courses at 20 different universities, 10 courses using Python, and 11 using C++. Each course used either the Python or C++ version of an online textbook from one publisher, each book having 100+ small coding exercises, expected to take 2-5 minutes each. We considered 11 exercises whose Python and C++ versions were nearly identical and that appeared in various chapters. We defined struggle rate for exercises, where struggle means a student spent excessive time or attempts on an exercise. Based on that rate, we found the learning for Python was not eased; in fact, Python students had significantly higher struggle rates than C++ students (26% vs. 13%). Higher rates were seen even when considering only classes with no prerequisites, classes for majors only, or classes for non-majors only. We encourage the community to do further analyses, to help guide teachers when choosing a CS 1 language.

This lightning talk presents new free, online material to provide new programmers with a solid foundation in debugging. Nearly every instructor who teaches programming notices that students have weak debugging skills. Faced with a failing program, many students make random changes and hope things improve. Or they shrug their shoulders, say "I have no idea what/s wrong", and ask an instructor for help. Most textbooks and websites provide insufficient coverage or training of debugging. This new material teaches a basic systematic process for debugging: Create a hypothesis, test the hypothesis, repeat. Seems obvious, but it/s not to most students. The material first teaches a general troubleshooting process using everyday systems, like smartphones can cars. With a solid foundation of the basic systematic process, the material then teaches basic debugging using a generic programming language. The material starts from the basics, following that adage that one must walk before they can run. Students typically don/t have the concept of "Hypothesize / Test". But after repeated examples that stress those items, they will hopefully have developed a habit of thinking of troubleshooting more systematically. The material is targeted at the fifth week of a CS1 course, when students have some programming experience and are beginning to face harder debugging challenges, but is also beneficial for any programming class beyond CS1, where it could be used in the first week. The material is delivered as free two-chapter online book available with sign in at http://www.zybooks.com/catalog/troubleshooting-basics/.

Network-connected embedded systems grow on a large scale as a critical part of Internet of Things, and these systems are under the risk of increasing malware. Anomaly-based detection methods can detect malware in embedded systems effectively and provide the advantage of detecting zero-day exploits relative to signature-based detection methods, but existing approaches incur significant performance overheads and are susceptible to mimicry attacks. In this article, we present a formal runtime security model that defines the normal system behavior including execution sequence and execution timing. The anomaly detection method in this article utilizes on-chip hardware to non-intrusively monitor system execution through trace port of the processor and detect malicious activity at runtime. We further analyze the properties of the timing distribution for control flow events, and select subset of monitoring targets by three selection metrics to meet hardware constraint. The designed detection method is evaluated by a network-connected pacemaker benchmark prototyped in FPGA and simulated in SystemC, with several mimicry attacks implemented at different levels. The resulting detection rate and false positive rate considering constraints on the number of monitored events supported in the on-chip hardware demonstrate good performance of our approach.

Accounting for all operating conditions of a system at the design stage is typically infeasible for complex systems. Monitoring and verifying system requirements at runtime enable a system to continuously and introspectively ensure the system is operating correctly in the presence of dynamic execution scenarios. In this article, we present a requirements-driven methodology enabling efficient runtime monitoring of embedded systems. The proposed approach extracts a runtime monitoring graph from system requirements specified using UML sequence diagrams. Non-intrusive, on-chip hardware dynamically monitors the system execution, verifies the execution adheres to the requirements model, and in the event of a failure provides detailed information that can be analyzed to determine the root cause. Using case studies of an autonomous vehicle and pacemaker prototypes, we analyze the relationship between event coverage, detection rate, and hardware requirements

Application profiling is an important step in the design and optimization of embedded systems. Accurately identifying and analyzing the execution of frequently executed computational kernels is needed to effectively optimize the system implementation, at both design time and runtime. Most previous profiling approaches are software based, which can incur significant overhead and may be prohibitive or impractical for profiling embedded systems at runtime. In addition, profiling methods typically focus on profiling the execution of specific tasks executing on a single core, but do not consider accurate and holistic profiling across multiple processor cores. Directly utilizing and naively combining isolated profiles from multiple processor cores can lead to significant profile inaccuracy. In this paper, we present a hardware-based dynamic application profiler for non-intrusively and accurately profiling software applications in multicore embedded systems. The profiler provides a detailed execution profile for computational kernels and maintains profile accuracy across multiple processor cores. The hardware-based profiler achieves an average error of less than 0.5% for the percentage execution time of profiled applications.

Network-connected embedded systems require multiple lines of defense against malware. In addition to preventing malware by designing secure interfaces and software, anomaly-based detection is needed to detect malware that successfully infiltrates these defenses. Timing based anomaly detection strengthens embedded system security by detecting anomalies in the execution time of critical software tasks. However, existing timing based anomaly detection methods use a lumped timing model that aggregates the timing of the software, processor architecture, operating system scheduling, etc., and thereby incurs significant variability. We present a non-intrusive hardware detector supporting two novel timing models, including a lumped timing multi-range model that clusters timing into multiple range bounds, and a subcomponent timing model that defines bounds for timing subcomponents of events. Timing subcomponents include intrinsic software execution, instruction cache misses, data cache misses, and interrupts. The experimental results demonstrate that the detection based on subcomponent timing model achieves greater malware detection accuracy compared to the lumped timing model without increasing false positives.

Getting students to read and study before class, to be better prepared for lecture, or to enable a flipped classroom is a long-standing difficulty for teachers of introductory programming classes. Furthermore, getting students to do homework, consisting of small practice problems and questions, is also a long-standing difficulty without massive grading resources. And even then, preventing students from copying others' solutions is difficult as well. Today, the web enables new interactive learning material that is replacing past forms of textbooks and homework assignments, and students today commonly have access to needed devices and the internet. This paper provides data on student reading and homework completion rates for web-based interactive learning material we created that automatically records reading and homework activity by students. The data is for several thousand students at over 10 universities, for introductory programming classes in Java, Python, and C++. The data shows that, with an appropriate amount of awarded points, required-reading completion rate was 84%, and auto-graded homework completion rate was 75%, varying somewhat based on how many course grade points those items were worth. Students on average spent about 10 minutes reading each section, and about 3 minutes per homework problem, both appropriate amounts for those items. Furthermore, we developed measures of whether students were earnestly attempting the reading and homeworks, versus just "cheating the system" to get course grade points. We describe those earnestness measures in this paper. With proper design and amount of assigned work, 80%-90% of students earnestly did the reading and homework activities, even when no penalty existed for cheating the system, and fewer than 3% blatantly cheated the system to get their points.

Data-adaptable embedded systems operate on a variety of data streams, which requires a large degree of configurability and adaptability to support runtime changes in data stream inputs. Data-adaptable reconfigurable embedded systems, when decomposed into a series of tasks, enable a flexible runtime implementation in which a system can transition the execution of certain tasks between hardware and software while simultaneously continuing to process data during the transition. Efficient runtime scheduling of task transitions is needed to optimize system throughput and latency of the reconfiguration and transition periods. In this article, we provide an overview of a runtime framework enabling the efficient transition of tasks between software and hardware in response to changes in system inputs. We further present and analyze several runtime transition scheduling algorithms and highlight the latency and throughput tradeoffs for two data-adaptable systems. To evaluate the task transition selection algorithms, a case study was performed on an adaptable JPEG2000 implementation as well as three other synchronous dataflow systems characterized by transition latency and communication load.

Complex sensing and decision applications such as object tracking and classification, video surveillance, unmanned aerial vehicle flight decisions, and others operate on vast data streams with dynamic characteristics. As the availability and quality of the sensed data changes, the underlying models and decision algorithms should continually adapt in order to meet desired high-level requirements. Due to the complexity of such dynamic data-driven systems, traditional design time techniques are often incapable of producing a solution that remains optimal in the face of dynamically changing data, algorithms, and even availability of computational resources. To assist developers of these systems, we present a modeling and optimization methodology that enables developers to capture application task flows and data sources, define associated quality metrics with data types, specify each algorithm's data and quality requirements, and define a data quality estimation framework to optimize the application at runtime. We demonstrate each facet of the modeling and optimization process via a video-based vehicle tracking and collision avoidance application, and show how such an approach results in efficient design space exploration when selecting the optimal set of algorithm modalities. When searching for an application configuration within 1% to 5% of optimal, our model-guided approach can achieve speedups of up to 9.3X versus a standard genetic algorithm and speedups of up to 80X relative to a brute force algorithm.

Recent research has demonstrated that many systems are vulnerable to numerous types of malicious activity. As the pervasiveness of embedded systems with network connectivity continues to increase, embedded systems security has become a critical challenge. However, most existing techniques for detecting malware utilize software-based methods that incur significant performance overheads that are often not feasible in embedded systems. In this paper, we present an overview of a novel method for non-intrusively detecting malware in embedded system. The proposed technique utilizes timing requirements to improve detection performance and provide increased resilience to mimicry attacks.

For textbooks on technical topics, the typical amount of text used is more than what many college students will read. Some teachers observe, and students report, that students commonly skim such text. As such, a writing style that aggressively minimizes text while still teaching the core technical topic may improve student learning; if text is short enough, students may then read and study the text more carefully. The objective of this study was to compare the effect of text quantity on amount learned. We created and compared content styles using a lesson that taught Google search techniques. The two main content styles were normal text and minimal text. The normal text style included 6-12 sentences followed by 1-3 examples. The minimal text style included 1-2 sentences followed by 1-3 examples. We conducted a randomized control study with 168 participants enrolled in a college-level Introduction to Computing course for non-computing majors. Each participant was randomly assigned one lesson style. We provided a pre-lesson and post-lesson quiz, each with ten questions. Additionally, the participants completed background and follow-up surveys. The study was part of a course homework assignment, so self-selection bias was limited. The course is primarily taken by non-majors and covers the basics of Word, Excel, and HTML. An improvement score is a participant's post-lesson minus pre-lesson quiz scores. The average improvement score for minimal text was 2.4 (6.5 - 4.1), which is higher (p-value <; 0.01) than the average improvement score for normal text of 1.1 (5.1 - 4.0). Thus, teaching the same topic using less text led to more learning. The conclusion is not that materials should be watered down, but rather that great attention should be paid to using minimal text while teaching the same core topics.

As the complexity of embedded systems rapidly increases, the use of traditional analysis and debug methods encounters significant challenges in monitoring, analyzing, and debugging the complex interactions of various software and hardware components. This situation is further exacerbated for in-situ debugging and verification in which traditional debug and trace interfaces that require physical access are unavailable, infeasible, or cost prohibitive. In this article, we present a system-level observation framework that provides minimally intrusive methods for dynamically monitoring and analyzing deeply integrated hardware and software components within embedded systems. The system-level observation framework monitors hardware and software events by inserting additional logic for detecting designer-specified events within hardware cores to observe complex interaction across hardware and software boundaries at runtime, and provides visibility for monitoring complex execution behavior of software applications without affecting the system execution.

The complexity of embedded systems presents key challenges for in-situ monitoring and analysis of complex hardware and software interactions. System-level observation methods have enabled nonintrusive runtime methods for monitoring this complex behavior across hardware and software boundaries and for deeply embedded components. Previous system-level observation methods utilized an efficient pipelined hardware architecture to ensure events are reported in-order based on the event occurrence. While providing high throughput for reporting events, this approach requires significant area resources. In this paper, we present an area-efficient event stream ordering technique that significantly reduces area requirements with tradeoff in event stream throughput.

With continuously shrinking technology, reliability issues such as Negative Bias Temperature Instability (NBTI) has resulted in considerable degradation of device performance, and eventually the short mean-time-to-failure (MTTF) of the whole multicore system. This article proposes a new workload balancing scheme based on device-level fractional NBTI model to balance the workload among active cores while relaxing stressed ones. Starting with NBTI-induced threshold voltage degradation, we define a concept of Capacity Rate (CR) as an indication of one core's ability to accept workload. Capacity rate captures core's performance variability in terms of delay and power metrics under the impact of NBTI aging. The proposed workload balancing framework employs the capacity rates as workload constraints, applies a Dynamic Zoning (DZ) algorithm to group cores into zones to process task flows, and then uses Dynamic Task Scheduling (DTS) to allocate tasks in each zone with balanced workload and minimum communication cost. Experimental results on a 64-core system show that by allowing a small part of the cores to relax over a short time period, the proposed methodology improves multicore system yield (percentage of core failures) by 20%, while extending MTTF by 30% with insignificant degradation in performance (less than 3%).

Discrete event system specification (DEVS) has been widely used within modeling and simulation to design, verify, and implement complex reactive systems. DEVS provides a robust formalism for designing systems using event-driven, state-based models in which timing information is explicitly defined. In this paper, we present an overview of a DEVS-based hardware design, synthesis, and optimization methodology. Within this approach, hardware DEVS (HDEVS) specifications can be synthesized to hardware, during which the event-driven model and explicit timing allow for an efficient hardware realization using globally asynchronous, locally synchronous design approach. Additionally, we present an optimization method for reducing power consumption through optimal frequency mapping and clock gating of individual components while ensuring system latency constraints are achieved. We further demonstrate the resulting power consumption savings for activity-driven forest fire and asthma health management applications targeting two low-power FPGA devices.

Data-adaptable reconfigurable embedded systems enable a flexible runtime implementation in which a system can transition the execution of tasks between hardware and software while simultaneously continuing to process data during the transition. Efficient runtime scheduling of task transitions is needed to optimize system throughput and latency of the reconfiguration and transition periods. In this paper, we present and analyze several runtime transition scheduling algorithms and highlight the latency and throughput tradeoffs for an example system.

The commercialization of sensor-based platforms is facilitating the realization of numerous sensor network applications with diverse application requirements. However, sensor network platforms are becoming increasingly complex to design and optimize due to the multitude of interdependent parameters that must be considered. To further complicate matters, application experts oftentimes are not trained engineers, but rather biologists, teachers, or agriculturists who wish to utilize the sensor-based platforms for various domain-specific tasks. To assist both platform developers and application experts, we present a centralized dynamic profiling and optimization platform for sensor-based systems that enables application experts to rapidly optimize a sensor network for a particular application without requiring extensive knowledge of, and experience with, the underlying physical hardware platform. In this article, we present an optimization framework that allows developers to characterize application requirements through high-level design metrics and fuzzy-logic-based optimization. We further analyze the benefits of utilizing dynamic profiling information to eliminate the guesswork of creating a “good” benchmark, present several reoptimization evaluation algorithms used to detect if re-optimization is necessary, and highlight the benefits of the proposed dynamic optimization framework compared to static optimization alternatives.

Significant research has demonstrated the performance and power benefits of runtime dynamic reconfiguration of FPGAs and microprocessor/FPGA devices. For dynamically reconfigurable systems, in which the selection of hardware coprocessors to implement within the FPGA is determined at runtime, online estimation methods are needed to evaluate the performance and power consumption impact of the hardware coprocessor selection. In this paper, we present a profile assisted online system-level performance and power estimation framework for estimating the speedup and power consumption of dynamically reconfigurable embedded systems. We evaluate the accuracy and fidelity of our online estimation framework for dynamic hardware kernel selection to maximize performance or minimize the system power consumption.

Technological advancements in wireless communications and embedded systems have led to the proliferation of wireless sensor network (WSN) applications, each with varying application requirements (i.e., lifetime, throughput, reliability, etc.). Sensor node tunable parameters enable WSN designers to specialize/tune a sensor node to meet application requirements, but however, parameter tuning is a challenging process that requires designer expertise to consider sensor node complexities and changing environmental stimuli. In this paper, we develop lightweight, online optimization algorithms for sensor node parameter tuning, which enables dynamic optimizations to meet application requirements and adapt to changing environmental stimuli. Results reveal that our online optimizations quickly converge to a near optimal solution using minimal computational and storage resources, and are thus amenable for implementation on resource and energy-constrained sensor nodes.

During the early design phases of software development, many developers use floating point data types and libraries but often convert these applications into fixed point representations in later design phases - a time consuming process often requiring significant designer effort. While various approaches have been proposed to automate the floating to fixed point conversion process, these approaches are mainly targeted at creating optimized software implementations and do not directly support partitioning floating point implementation to hardware. We present an approach to optimize the number of bits required for a dynamically adaptable fixed-point representation using SNR analysis methods targeting computationally intensive floating-point kernels. We present a hardware/software partitioning methodology that leverages this SNR analysis to partition application kernels to custom hardware coprocessors implemented within a field-programmable gate array. Using several case study applications, we highlight the performance benefits and area requirements of the resulting hardware implementations.

The deep integration of software and hardware components within complex system-on-chip (SOC) designs prevents the use of traditional analysis and debug methods to observe the internal state of these components. This situation is further exacerbated for in-situ debugging, verification, and certification efforts in which physical access to traditional debug and trace interfaces is unavailable, infeasible, or cost prohibitive. In this paper, we present an overview of an event-driven system-level observation framework that provides low-overhead methods for observing and analyzing designer specified hardware and software events at runtime.

This article aims to achieve computational reliability and energy efficiency through codevelopment of algorithms, device, and circuit designs for application-specific, reconfigurable architectures. The new methodology characterizes aging-switching activity and aging-supply voltage relationships that are applicable for minimizing power consumption and task execution efficiency in order to achieve low bit energy ratio (BER). In addition, a new dynamic management algorithm (DMA) is proposed to alleviate device degradation and to extend system lifespan. In contrast to traditional workload balancing schemes in which cores are regarded as homogeneous, the new algorithm ranks cores as “highly competitive,” “less competitive,” and “not competitive” according to their various competitiveness. Core competitiveness is evaluated based upon their reliability, temperature, and timing requirements. Consequently, “competitive” cores will take charge of the majority of the tasks at relatively high voltage/frequency without violating power and timing budgets, while “not competitive” cores will have light workloads to ensure their reliability. The new approach combines intrinsic device characteristics (aging-switching activity and aging-supply voltage curves) into an integrated framework to achieve high reliability and low energy level with graceful degradation of system performance. Experimental results show that the proposed method has achieved up to 20% power reduction, with about 4% performance degradation (in terms of accomplished workload and system throughput), compared with traditional workload balancing methods. The new method also improves system mean-time-to-failure (MTTF) by up to 25%.

Significant research has demonstrated the performance and power benefits of runtime dynamic reconfiguration of FPGAs and microprocessor/FPGA devices. For dynamically reconfigurable systems, in which the selection of hardware coprocessors to implement within the FPGA is determined at runtime, online estimation methods are needed to evaluate the performance and power consumption impact of the hardware coprocessor selection. In this paper, we present a profile assisted online system-level performance and power estimation framework for estimating the speedup and power consumption of dynamically reconfigurable embedded systems. We evaluate the accuracy and fidelity of our online estimation framework for dynamic hardware kernel selection to maximize performance or minimize system power consumption.

Application profiling—the process of monitoring an application to determine the frequency of execution within specific regions—is an essential step within the design process for many software and hardware systems. Profiling is often a critical step within hardware/software partitioning utilized to determine the critical kernels of an application. In this article, we present an innovative, nonintrusive dynamic application profiler (DAProf) capable of profiling an executing application by monitoring the application's short backward branches, function calls, and function returns. The resulting profile information provides an accurate characterization of the frequently executed loops within the application providing a breakdown of loop executions versus loop iterations per execution. DAProf achieves excellent profiling accuracy with an average accuracy of 98% for loop executions, 97% for average iterations per execution, and 95% for percentage of execution time. In addition, the presented dynamic application profiler incurs as little as 11% area overhead compared to an ARM9 microprocessor. DAProf is ideally suited for rapidly profiling software applications and dynamic optimization approaches such as dynamic hardware/software partitioning in which detailed loop execution information is needed to provide accurate performance estimates.

As device feature sizes continue to shrink, long-term reliability such as Negative Bias Temperature Instability (NBTI) leads to low yields and short mean-time-to-failure (MTTF) in multi-core systems. This paper proposes a new workload balancing scheme based on device level fractional NBTI model to balance the workload among active cores while relaxing stressed ones. The proposed method employs the Capacity Rate (CR) provided by the NBTI model, applies Dynamic Zoning (DZ) algorithm to group cores into zones to process task flows, and then uses Dynamic Task Scheduling (DTS) to allocate tasks in each zone with balanced workload and minimum communication cost. Experimental results on 64-core system show that by allowing a small part of the cores to relax over a short time period (10 seconds), the proposed methodology improves multi-core system yield (percentage of core failures) by 20%, while extending MTTF by 30% with insignificant degradation in performance (less than 3%).

This paper introduces a new methodology that characterizes aging-duty cycle and aging-supply voltage relationships that are applicable to minimizing power consumption and task execution time to achieve low Bit-Energy-Ratio (BER). In contrast to the traditional workload balancing scheme where cores are regarded as homogeneous, we proposed a new task scheduler that ranks cores according to their various competitiveness evaluated based upon their reliability, temperature and timing requirements. Consequently, the new approach combines internal characteristics (aging-duty cycle and aging-supply voltage curves) into an integrated framework to achieve system performance improvement or graceful degradation with high reliability and low power. Experimental results show that the proposed method has achieved 18% power reduction with about 4% performance degradation (in terms of accomplished workload) compared with traditional workload balancing methods.

Technological advancements in embedded systems due to Moore's law have lead to the proliferation of wireless sensor networks (WSNs) in different application domains (e.g. defense, health care, surveillance systems) with different application requirements (e.g. lifetime, reliability). Many commercial-off-the-shelf (COTS) sensor nodes can be specialized to meet these requirements using tunable parameters (e.g. voltage, frequency) to specialize the operating state. Since a sensor node's performance depends greatly on environmental stimuli, dynamic optimizations enable sensor nodes to automatically determine their operating state in-situ. However, dynamic optimization methodology development given a large design space and resource constraints (memory and computational) is a very challenging task. In this paper, we propose a lightweight dynamic optimization methodology that intelligently selects initial tunable parameter values to produce a high-quality initial operating state in one-shot for time-critical or highly constrained applications. Further operating state improvements are made using an efficient greedy exploration algorithm, achieving optimal or near-optimal operating states while exploring only 0.04% of the design space on average.

Dynamically reconfigurable field-programmable gate arrays (FPGAs) hold the promise of providing a virtual hardware resource in which hardware circuits can be dynamically scheduled onto the available FPGA resources. However, reconfiguring an FPGA can incur significant performance and energy overheads. This paper analyzes the relationship between several hardware task scheduling algorithms and their impact on the number of reconfigurations required to execute a set of hardware tasks. In addition, three new hardware scheduling algorithms, specifically designed to reduce the number of required reconfigurations, are presented and analyzed. By selectively locking configurations within the reconfigurable tiles of an FPGA, significant reductions in the number of required reconfiguration can be achieved.

Application profiling – the process of monitoring an application to determine the frequency of execution within specific regions – is an essential step within the design process for many software and hardware systems. Profiling is often a critical step within hardware/software partitioning utilized to determine the critical kernels of an application. In this paper, we present a non-intrusive dynamic application profiler (DAProf) capable of profiling an executing application by monitoring the application’s short backwards branches, function calls, function returns, as well as efficiently detecting context switches to provide accurate characterization of the frequently executed loops within multitasked applications. DAProf can accurately profile multiple tasks within a software application with 98.5 % accuracy using as little as 10 % additional area compared to an ARM9 processor.

While soft processor cores provided by FPGA vendors offer designers with increased flexibility, such processors typically incur penalties in performance and energy consumption compared to hard processor core alternatives. The recently developed technology of warp processing can help reduce those penalties. Warp processing is the dynamic and transparent transformation of critical software regions from microprocessor execution to much faster circuit execution on an FPGA. In this article, we describe an implementation of a warp processor on a Xilinx Virtex-II Pro and Spartan3 FPGAs incorporating one or more MicroBlaze soft processor cores. We further provide a detailed analysis of the energy overhead of dynamically partitioning an application's kernels to hardware executing within an FPGA. Considering an implementation that periodically partitions the executing application once every minute, a MicroBlaze-based warp processor implemented on a Spartan3 FPGA achieves average speedups of 5.8× and energy reductions of 49% compared to the MicroBlaze soft processor core alone—providing competitive performance and energy consumption compared to existing hard processor cores.

Warp processing is a recent computing technology capable of autonomously partitioning the critical kernels within an executing software application to hardware circuits implemented within an on-chip FPGA. While previous performance-driven warp processing has been shown to provide significant performance improvements over software only execution, the dynamic performance improvement of warp processors may be lost for certain application domains, such as real-time systems. Alternatively, as power consumption continue to become a dominant design constraint, we present and thoroughly analyze a low-power warp processing methodology that leverages voltage and/or frequency scaling to substantially reduce power consumption without any performance degradation—all without requiring designer effort beyond the initial software development.

Application profiling - the process of monitoring an application to determine the frequency of execution within specific regions - is an essential step within the design process for many software and hardware systems. In this paper, we present an efficient innovative, non-intrusive dynamic application profiler (DAProf) capable of profiling an executing application by monitoring the application's short backwards branches and providing detailed profiling statistics for characterizing loop execution behavior. DAProf is ideally suited for hardware/software partitioning approaches in which detailed loop execution information is needed to provide accurate performance estimates. DAProf provides a profiling accuracy of greater than 90% with only an 11% area overhead compared to a small ARM9.

Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels within the software as custom hardware circuits in an on-chip FPGA. However, the original warp processor design was primarily performance-driven and did not focus on power consumption, which is becoming an increasingly important design constraint. Focusing on power consumption, we present an alternative low-power warp processor design and methodology that can dynamically and transparently reduce power consumption of an executing application with no degradation in system performance, achieving an average reduction in power consumption of 74%. We further demonstrate the flexibility of this approach to provide dynamic control between high-performance and low-power consumption

Soft-core microprocessors mapped onto field-programmable gate arrays (FPGAs) represent an increasingly common embedded software implementation option. Modern FPGA soft-cores are parameterized to support application-specific customization, wherein pre-defined units, such as a multiplication unit or floating-point unit, may be included in the microprocessor architecture to speed up software execution at the expense of increased size. We introduce a methodology for fast applicationspecific customization of a parameterized FPGA soft core, using synthesis and execution to obtain size and performance data in order to create a tool that can be used across a variety of tool platforms and FPGA devices. As synthesizing a soft core takes tens of minutes, developing heuristics that execute in an acceptable time of an hour or two, yet find near-optimal results, is

Soft-core programmable processors on field-programmable gate arrays (FPGAs) can be custom synthesized to instantiate only those hardware units, such as multipliers and floating-point units, that an application requires to meet performance demands, thus minimizing soft-core size on the FPGA. Conjoining processors, meaning to share hardware units among two or more processors, can further reduce soft-core size, leaving more resources for other circuits such as custom coprocessors. Using Xilinx MicroBlaze coprocessors and standard embedded system benchmarks, we show that conjoining two processors can provide 16% processor size reductions on average, with less than 1% cycle count overhead. We introduce an efficient dynamic-programming-based exploration method to find the best custom instantiation of hardware units, considering both standalone and conjoined options, for soft-core processors.

We describe a new processing architecture, known as a warp processor, that utilizes a field-programmable gate array (FPGA) to improve the speed and energy consumption of a software binary executing on a microprocessor. Unlike previous approaches that also improve software using an FPGA but do so using a special compiler, a warp processor achieves these improvements completely transparently and operates from a standard binary. A warp processor dynamically detects the binary's critical regions, reimplements those regions as a custom hardware circuit in the FPGA, and replaces the software region by a call to the new hardware implementation of that region. While not all benchmarks can be improved using warp processing, many can, and the improvements are dramatically better than those achievable by more traditional architecture improvements. The hardest part of warp processing is that of dynamically reimplementing code regions on an FPGA, requiring partitioning, decompilation, synthesis, placement, and routing tools, all having to execute with minimal computation time and data memory so as to coexist on chip with the main processor. We describe the results of developing our warp processor. We developed a custom FPGA fabric specifically designed to enable lean place and route tools, and we developed extremely fast and efficient versions of partitioning, decompilation, synthesis, technology mapping, placement, and routing. Warp processors achieve overall application speedups of 6.3X with energy savings of 66% across a set of embedded benchmark applications. We further show that our tools utilize acceptably small amounts of computation and memory which are far less than traditional tools. Our work illustrates the feasibility and potential of warp processing, and we can foresee the possibility of warp processing becoming a feature in a variety of computing domains, including desktop, server, and embedded applications.

Field programmable gate arrays (FPGAs) provide designers with the ability to create hardware circuits quickly. Increases in FPGA configurable logic capacity and decreasing FPGA costs have enabled designers to incorporate FPGAs more readily in their designs. FPGA vendors have begun providing configurable soft processor cores that can be synthesized onto their FPGA products. While FPGAs with soft processor cores provide designers with increased flexibility, such processors typically have degraded performance and energy consumption compared to hard-core processors. Previously, we proposed warp processing, a technique capable of optimizing a software application by dynamically and transparently re-implementing critical software kernels as custom circuits in on-chip configurable logic. We now study the potential of a MicroBlaze soft-core based warp processing system to eliminate the performance and energy overhead of a soft-core processor compared to a hard-core processor. We demonstrate that the soft-core based warp processor achieves average speedups of 5.8 and energy reductions of 57% compared to the soft core alone. Our data shows that a soft-core based warp processor yields performance and energy consumption competitive with existing hard-core processors, thus expanding the usefulness of soft processor cores on FPGAs to a broader range of applications.

Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously introduced the concept of a standard hardware binary, using a just-in-time compiler to compile the hardware binary to a field-programmable gate array (FPGA). Our JIT compiler includes lean versions of technology mapping, placement, and routing algorithms, of which routing is the most computationally and memory expensive step. As FPGAs continue to increase in size, a JIT FPGA compiler must be capable of efficiently mapping increasingly larger hardware circuits. In this paper, we analyze the scalability of our lean on-chip router, the Riverside on-chip router (ROCR), for routing increasingly large hardware circuits. We demonstrate that ROCR scales well in terms of execution time, memory usage and circuit quality, and we compare the scalability of ROCR to the well known versatile place and route (VPR) timing-driven routing algorithm, comparing to both their standard routing algorithm and their fast routing algorithm. Our results show that on average ROCR executes 3 times faster using 18 times less memory than VPR. ROCR requires only 1% more routing resources, while creating a critical path 30% longer VPR's standard timing-driven router. Furthermore, for the largest hardware circuit, ROCR executes 3 times faster using 14 times less memory, and results in a critical path 2.6% shorter than VPR's fast timing-driven router.

Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures, yielding software portability benefits. We previously introduced the concept of a standard hardware binary to achieve similar portability benefits for hardware, using a JIT compiler to compile the hardware binary to an FPGA. Our JIT compiler includes lean versions of technology mapping, placement, and routing algorithms that implement the standard hardware binary on a simple custom FPGA fabric designed specifically for JIT compilation. While directly implementing a custom FPGA fabric on silicon may be feasible for some applications, we investigated the option of implementing the simple FPGA fabric as a circuit mapped to a physical FPGA - a virtual FPGA. We described our simple fabric in structural VHDL, synthesized the fabric onto a Xilinx Spartan-IIE FPGA, and mapped 18 benchmark circuits onto the resulting virtual FPGA. Our results show a 6X decrease in performance and a 100X increase in hardware resource usage for the virtual FPGA approach compared to mapping the circuits directly to the physical FPGA. For applications in which hardware portability is essential, a designer could leverage the large capacity of current commercially available FPGAs to implement a virtual FPGA with tens of thousands of configurable gates, providing about the same amount of configurable logic as FPGAs produced in the mid 1990s. Nevertheless, the large overheads clearly indicate the need to develop a virtual FPGA approach tuned to physical fabrics in order to reduce the overhead.

Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. However, embedded systems increasingly incorporate Field Programmable Gate Arrays (FPGAs), for which the concept of a standard hardware binary did not previously exist, requiring designers to implement a hardware circuit for a single specific FPGA. We introduce the concept of a standard hardware binary, using a just-in-time compiler to compile the hardware binary to an FPGA. A JIT compiler for FPGAs requires the development of lean versions of technology mapping, placement, and routing algorithms, of which routing is the most computationally and memory expensive step. We present the Riverside On-Chip Router (ROCR) designed to efficiently route a hardware circuit for a simple configurable logic fabric that we have developed. Through experiments with MCNC benchmark hardware circuits, we show that ROCR works well for JIT FPGA compilation, producing good hardware circuits using an order of magnitude less memory resources and execution time compared with the well known Versatile Place and Route (VPR) tool suite. ROCR produces good hardware circuits using 13X less memory and executing 10X faster than VPR's fastest routing algorithm. Furthermore, our results show ROCR requires only 10% additional routing resources, and results in circuit speeds only 32% slower than VPR's timing-driven router, and speeds that are actually 10% faster than VPR's routability-driven router.

In previous work, we showed the benefits and feasibility of having a processor dynamically partition its executing software such that critical software kernels are transparently partitioned to execute as a hardware coprocessor on configurable logic - an approach we call warp processing. The configurable logic place and route step is the most computationally intensive part of such hardware/software partitioning, normally running for many minutes or hours on powerful desktop processors. In contrast, dynamic partitioning requires place and route to execute in just seconds and on a lean embedded processor. We have therefore designed a configurable logic architecture specifically for dynamic hardware/software partitioning. Through experiments with popular benchmarks, we show that by specifically focusing on the goal of software kernel speedup when designing the FPGA architecture, rather than on the more general goal of ASIC prototyping, we can perform place and route for our architecture 50 times faster, using 10,000 times less data memory, and 1,000 times less code memory, than popular commercial tools mapping to commercial configurable logic. Yet, we show that we obtain speedups (2x on average, and as much as 4x) and energy savings (33% on average, and up to 74%) when partitioning even just one loop, which are comparable to commercial tools and fabrics. Thus, our configurable logic architecture represents a good candidate for platforms that will support dynamic hardware/software partitioning, and enables ultra-fast desktop tools for hardware/software partitioning, and even for fast configurable logic design in general.

Memory access can account for about half of a microprocessor system's power consumption. Customizing a microprocessor cache's total size, line size and associativity to a particular program is well known to have tremendous benefits for performance and power. Customizing caches has until recently been restricted to core-based flows, in which a new chip will be fabricated. However, several configurable cache architectures have been proposed recently for use in pre-fabricated microprocessor platforms. Tuning those caches to a program is still however a cumbersome task left for designers, assisted in part by recent computer-aided design (CAD) tuning aids. We propose to move that CAD on-chip, which can greatly increase the acceptance of configurable caches. We introduce on-chip hardware implementing an efficient cache tuning heuristic that can automatically, transparently, and dynamically tune the cache to an executing program. We carefully designed the heuristic to avoid any cache flushing, since flushing is power and performance costly. By simulating numerous Powerstone and MediaBench benchmarks, we show that such a dynamic self-tuning cache can reduce memory-access energy by 45% to 55% on average, and as much as 97%, compared with a four-way set-associative base cache, completely transparently to the programmer.

Memory accesses often account for about half of a microprocessor system's power consumption. Customizing a microprocessor cache's total size, line size, and associativity to a particular program is well known to have tremendous benefits for performance and power. Customizing caches has until recently been restricted to core-based flows, in which a new chip will be fabricated. However, several configurable cache architectures have been proposed recently for use in prefabricated microprocessor platforms. Tuning those caches to a program is still, however, a cumbersome task left for designers, assisted in part by recent computer-aided design (CAD) tuning aids. We propose to move that CAD on-chip, which can greatly increase the acceptance of tunable caches. We introduce on-chip hardware implementing an efficient cache tuning heuristic that can automatically, transparently, and dynamically tune the cache to an executing program. Our heuristic seeks not only to reduce the number of configurations that must be examined, but also traverses the search space in a way that minimizes costly cache flushes. By simulating numerous Powerstone and MediaBench benchmarks, we show that such a dynamic self-tuning cache saves on average 40% of total memory access energy over a standard nontuned reference cache.

We introduce a novel memory architecture that can count the occurrences of patterns on a system's bus, a task known as profiling. Such profiling can serve a variety of purposes, like detecting a microprocessor's software hot spots or frequently used data values, which can be used to optimize various aspects of the system. The memory, which we call ProMem, is based on a pipelined binary search tree structure, yielding several beneficial features, including nonintrusiveness, accurate counts, excellent size and power efficiency, very fast access times, and the use of standard memories with only simple additional logic. The main limitation is that the set of potential patterns must be preloaded into the memory. We describe the ProMem architecture, and show excellent size and performance advantages compared with content-addressable memory (CAM) based designs.

While Boolean logic minimization is typically used in logic synthesis, logic minimization can be useful in numerous other applications. However, many of those applications, such as Internet Protocol routing table and network access control list reduction, require logic minimization during the application's runtime, and hence could benefit from minimization executing on-chip alongside the application. On-chip minimization can even enable dynamic hardware/software partitioning. We discuss requirements of on-chip logic minimization, and present our new on-chip logic minimization tool, ROCM. We compare with the well-known Espresso logic minimizer and show that ROCM is 10 times smaller, executes 10-20 times faster, and uses 3 times less data memory, with a mere 2% quality penalty, for the routing table and access control list applications. We show that ROCM solves real-sized problems on an ARM7 embedded processor in just seconds.

Partitioning an application among software running on a microprocessor and hardware co-processors in on-chip configurable logic has been shown to improve performance and energy consumption in embedded systems. Meanwhile, dynamic software optimization methods have shown the usefulness and feasibility of runtime program optimization, but those optimizations do not achieve as much as partitioning. We introduce a first approach to dynamic hardware/software partitioning. We describe our system architecture and initial on-chip tools, including profiler, decompiler, synthesis, and placement and routing tools for a simplified configurable logic fabric, able to perform dynamic partitioning of real benchmarks. We show speedups averaging 2.6 for five benchmarks taken from Powerstone, NetBench, and our own benchmarks.

Profiling an application executing on a microprocessor is part of the solution to numerous software and hardware optimization and design automation problems. Most current profiling techniques suffer from runtime overhead, inaccuracy, or slowness, and the traditional non-intrusive method of using a logic analyzer doesn't work for today's system-on-a-chip having embedded cores. We introduce a novel on-chip memory architecture that overcomes these limitations. The architecture, which we call ProMem, is based on a pipelined binary tree structure. It achieves single-cycle throughput, so it can keep up with today's fastest pipelined processors. It can also be laid out efficiently and scales very well, becoming more efficient the larger it gets. The memory can be used in a wide-variety of common profiling situations, such as instruction profiling, value profiling, and network traffic profiling, which in turn can be used to guide numerous design automation tasks.

Reuse of cores can reduce design time for systems-on-a-chip. Such reuse is dependent on being able to easily interface a core to any bus. To enable such interfacing, many propose separating a core's interface from its internals by using a bus wrapper. However, this separation can lead to a performance penalty when reading a core's internal registers. In this paper, we introduce prefetching, which is analogous to caching, as a technique to reduce or eliminate this performance penalty, involving a tradeoff with power and size. We describe the prefetching technique, classify different types of registers, describe our initial prefetching architectures and heuristics for certain classes of registers, and highlight experiments demonstrating the performance improvements and size/power tradeoffs. We further introduce a technique for automatically designing a prefetch unit that satisfies user-imposed register-access constraints. The technique benefits from mapping the prefetching problem to the well-known real-time process scheduling problem. We then extend the technique to allow user-specified register interdependencies, using a Petri net model, resulting in even more efficient prefetch schedules.

We describe an automated environment to assist a system-on-achip designer to tune a microprocessor core to a particular application program that will run on the microprocessor, and vice-versa, with the goal of reducing embedded system power consumption.We limit such tuning to modifications that do not change the microprocessor instruction set, thus avoiding the large costs that would come with such a change.Our tuning environment for the 8051 microcontroller is freely-available on the web.

Today's system-on-a-chip designs consist of many cores, To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic separated from their wrapper. This separation may introduce extra read latency. Pre-fetching register data into register copies in the bus wrapper can reduce or eliminate this extra latency. In this paper, we introduce a technique for automatically designing a pre-fetch unit that satisfies user-imposed register-access constraints. The technique benefits from mapping the pre-fetching problem to the well-known real-time process scheduling problem. We then extend the technique to allow user-specified register interdependencies, using a Petri net model, resulting in even more efficient pre-fetch schedules.