This paper introduces an on-chip hybrid rectifier tailored for RF energy harvesting at 2.4 GHz. Leveraging advancements in CMOS technology, this solution offers a novel approach to powering devices, particularly suitable for implantable biomedical devices and applications. This proposed architecture features 3-stage reconfigurable hybrid rectifiers, with each stage comprising a regular threshold voltage ($V_{th}$) MOS rectifier for high input power and a low ($V_{th}$) MOS rectifier for low input power. The cross-coupled connection of both rectifiers ensures minimal ON-resistance and low reverse leakage current during forward and reverse biased conditions, respectively. Through effective reconfiguration of power paths, the proposed system achieves high power conversion efficiency across a broad input power range. This proposed system is designed and Implemented in UMC$0.18~\mu $m CMOS technology with a Wi-Fi frequency of (2.4 GHz), the measured results are demonstrating an efficiency exceeding >35% for input power levels ranging from −23 dBm to −12 dBm, driving a load of 40 K$\Omega $.

This paper presents a dual voltage controlled oscillator (VCO) based integer-N phase locked loop (PLL) for navigation receiver operating at L 5-band and S-band. The PLL incorporates a multiplexer based extended range multi modulus divider (MMD) in the feedback path to cater to both L 5 and S band. Fabricated in UMC 65-nm CMOS, the PLL consumes 7.9 mW power from 1.0 V supply. The PLL achieves a phase-noise (PN) of −121 dBc/Hz and −120 dBc/Hz at 1 MHz offset for L 5 band and S-band, respectively achieving a best figure-of-merit (FoM) of 179.9 dBc/Hz.

The design and detailed analysis of a Reconfigurable concurrent Dual-band LNA with Dynamic Output Load Network operating in 0.9GHz and 1.8GHz has been demonstrated in 0.18um CMOS process. A common source (CS) cascade topology with serial and parallel LC circuit based input matching was adopted. A new output load network made reconfigurable in terms of high gain(HG) and low gain(LG) mode through the output impedance seen at the respective nodes. The impedance nodes are controlled through control (CTHand CTL) switches. Varactor tuning has been incorporated to input and output to optimize the circuit. The proposed LNA achieves a S21of 19 dB and 13 dB at 0.9 GHz and 1.8 GHz for high gain mode, and simultaneously 10 dB and 7 dB gain for low gain mode. The extracted simulations shows with noise figure (NF) of 4 dB and 4.2 dB at high gain mode and 3.3 dB and 4 dB at low gain mode respectively.

In this paper, a burst mode constant ON-time-controlled, energy harvesting charger is presented. The proposed boost converter system uses the burst mode control to improve the efficiency by 11%, compared to the conventional single-mode energy transfer implementation with an ultralow-power input comparator. A technique to deduce an optimum inductor energizes time across the given input range, for which the maximum converter efficiency is demonstrated. An internally triggered, capacitor-less sample-and-hold block addresses the leakage issue in the conventional fractional open-circuit voltage maximum power point tracking systems. The system is capable of charging a super-capacitor of 4.7 mF, from 1.8 to 3.3 V from an input power of 50 μW to 100 mW by maintaining the maximum power at the input. The entire system is designed and fabricated in the standard 180-nm CMOS technology, and the measurement results show a peak efficiency of 92% at 98-mW input power for the output voltage of 3 V and efficiency ≥65% across the range of input voltages more than 0.3 V for the output voltage of 1.8 V.

This article proposes a low-power reconfigurable multimode low-noise amplifier (LNA) that can be configured for multiple narrowband as well as wideband operations while providing simultaneous input matching and output load reconfigurabilty. A component sharing technique and a component-Q-aware impedance-matching technique are introduced in the proposed LNA circuit. The proposed LNA, implemented in a United Microelectronics Corporation (UMC) 0.18-μm CMOS process, can operate in a narrowband mode with center frequencies around 1.8, 2.1, and 2.4 GHz as well as in a wideband mode (2-5 GHz). Measured results show that the LNA has achieved 14.1, 14.5, and 14.1 dB of voltage gain, 8.5, 8.2, and 8.7 dB of noise figure (NF) in 1.8-, 2.1-, and 2.4-GHz modes, respectively. In the wideband mode, the measured gain and the NF are 14.5 and 7.8 dB, respectively. The LNA consumes 2 and 3.8 mW of power from the 1.8-V supply in the narrowband and wideband modes, respectively.

An Event Triggerred - Fractional Open Circuit Voltage Maximum Power Point Tracking (ET-FOCV MPPT) technique is introduced for irradiance change aware open-circuiting in FOCV systems. The ET-FOCV scheme is implemented using a novel Irradiance Change Detection (ICD) block which is based on gradient based current sensing technique. By avoiding the periodic open circuiting in the absence of irradiance change, this technique extracts more energy than the conventional FOCV systems. The proposed ICD block can operate from 10 Hz to 100 kHz system clock frequencies targeting micro scale energy harvesting systems. With the ICD block and ET-FOCV technique, the proposed solar energy harvesting system harvests energy from input power level of 200 μW to 20 mW and input voltage level of 100 mV to 1.5 V and charges a battery to 3.3 V by boost operation. The entire system is implemented in standard 180 nm CMOS technology and the extracted results validate the system performance.

In this paper, a burst mode constant ON-time-controlled, energy harvesting charger is presented. The proposed boost converter system uses the burst mode control to improve the efficiency by 11%, compared to the conventional single-mode energy transfer implementation with an ultralow-power input comparator. A technique to deduce an optimum inductor energizes time across the given input range, for which the maximum converter efficiency is demonstrated. An internally triggered, capacitor-less sample-and-hold block addresses the leakage issue in the conventional fractional open-circuit voltage maximum power point tracking systems. The system is capable of charging a super-capacitor of 4.7 mF, from 1.8 to 3.3 V from an input power of 50 μW to 100 mW by maintaining the maximum power at the input. The entire system is designed and fabricated in the standard 180-nm CMOS technology, and the measurement results show a peak efficiency of 92% at 98-mW input power for the output voltage of 3 V and efficiency ≥65% across the range of input voltages more than 0.3 V for the output voltage of 1.8 V.

A human body heat driven thermal energy harvesting regulator with high output power at low input voltages and small form factor, suitable to power compact and feature-packed wearable biomedical Internet of Things (IoT) nodes, is developed in this paper. The system demonstrates$2.3{\times }$higher throughput than prior art at low input voltages with a maximum conversion ratio of$83 \times $, in order to support complex and power hungry IoT operations like onboard processing and data transmission. The peak load supportable by the system is extended by utilizing maximum power extraction and minimizing converter losses in a single-stage compact power management unit. A fixed-frequency technique, independent of input voltage variation is proposed to maximize output power when load demands. A digital switch controller with ultra low power digitally controllable delay circuit is implemented to perform zero current switching to improve efficiency. The system, fabricated in 180-nm standard CMOS process, operates from open circuit input voltages ranging from 25 to 210 mV while supplying a regulated 1 V output. The functionality of the system is demonstrated in real-time by integrating the regulator with an emulated cardiac monitoring IoT node. The system delivers a peak power of 1.03 mW at open circuit voltage of the transducer,${V} _{\text {TEG}}$, of 210 mV, generated at body to ambient temperature difference of ~8 °C. The total area occupied by the system is 0.13 mm2and has an end-to-end peak efficiency of 65% at${V} _{\text {TEG}}$of 50 mV in measurement.

This paper proposes a novel method for ripple cancellation in multi-phase converters. Unlike the conventional multi-phase converter, the proposed topology can cancel the ripple irrespective of the duty ratios. The proposed topology is designed to give 3.3V output for wide supply range of 4.5 to 18V and load range of 0 to 3A in AMS 0.35um high-voltage CMOS process. Transistor level simulation results validate that the proposed method can reduce the ripple by 80% in a multi-phase converter. Cancelling the current ripple at the output allows the inductors and capacitors to be sized much smaller compared to the state of the art reported designs.

This work proposes an energy efficient wearable CMOS biomedical signal acquisition and digitization scheme powered by RF energy harvesting circuit. The system consists of a ultra-low power analog front end (AFE) incorporating low noise instrumentation amplifier (IA)(CMRR=75dB), two programmable gain amplifiers (PGA), mixed signal automatic gain control (AGC) and a successive approximation register (SAR) analog to digital converter (ADC)(10-bit). The full system is powered by a power aware RF energy harvesting circuit for an input range of -26dBm to -8dBm. The AFE along with ADC consumes 343nA with 1V supply voltage in UMC 0.18μm CMOS technology.

This paper presents, a complete energy harvesting system with improved implementation of Fractional Open Circuit Voltage (FOCV) technique, to mitigate obligation of using off chip sampling capacitor, gratuitous periodic open circuit operation for Maximum Power Point Extraction (MPP) from solar cell. A possible solution to minimize the reverse current in solar cell due to abrupt decline in irradiance is also proposed. Thus, usual off-chip sampling capacitance can be effectively replaced by on-chip capacitance as low as 3.75pF. Entire system is implemented in 180nm CMOS technology and the proposed blocks consumes 0.675mm × 0.425mm area and an average power of 340nW.

A maximum power point tracking DC-DC boost converter and reconfigurable rectifier to harvest energy from ambient RF source in an auto-configurable mixed converter mode is presented. A reconfigurable rectifier with adjustable rectifier stages in the high input power range(-16dBm to -8dBm) and a boost converter with adaptive control in the low input power level range(-26dBm to -17dBm) to maximize the efficiency is proposed. The system is designed at UHF band(900MHz) to drive a load with 1V and shows a peak efficiency of 62.8% at -20dBm and 78.2% at -12dBm and it is implemented using UMC 0.18μm CMOS technology.

This paper presents a low power reconfigurable narrowband, concurrent multiband, wideband multimode LNA for multi-standard applications. Subthreshold region biasing, quality factor aware impedance matching, component sharing between different modes are employed. Input matching is unbounded from other performance parameter. Proposed LNA works in narrowband mode at 1.8GHz, 2.1GHz and 2.4GHz, dualband mode at 1.9GHz and 5.4GHz and in wideband mode 2-5GHz. The voltage gain varies from 11dB to 18dB, noise figure from 5.5dB to 8.5dB and CP1dB -9.2dBm to -17.4dBm over different modes, while consuming 1.8mW in narrowband and 3.84mW in other modes from 1.8V supply in UMC180nm CMOS process.

A novel wide band low power low noise amplifier using subthreshold technique is presented in this paper. This LNA built with Common-Gate (CG) input stage for wide band input matching and a Common Source (CS) - Common Gate (CG) cascode stage for gain boosting. Power reduction is achieved by driving the front end CG transistor in sub-threshold region and input matching is done by LC circuit instead of traditional CG method (Rs=1/gm). The circuit is simulated using Spectra-RF simulator in 0.18μm CMOS technology, and achieved 13.5-14.5 dB (7.5 to 8.5 dB + 6dB loss in buffer) gain over entire band of 1.5-7.5GHz with a 5-10.5dB NF while consuming 4.9mW of power from 1.8V supply.