Demo Data from EDBT 2026 / reviewers in the wild / expert
Homayoon Sam
dblp:44/2073
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1990
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 67% Integrated circuit design · 33% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture
computer arithmetic |
0.0 | 1 | 1990 | A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations · IEEE Trans. Computers 1990 |
Integrated circuit design › digital circuit design › arithmetic circuit design
multiplier design |
0.0 | 1 | 1990 | A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations · IEEE Trans. Computers 1990 |
Processor architecture and microarchitecture › computer arithmetic
signed digit representation |
0.0 | 1 | 1990 | A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations · IEEE Trans. Computers 1990 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1990 | A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier ImplementationsabstractA multibit recoding algorithm for signed two's complement binary numbers is presented and proved. In general, a k+1-bit recoding will result in a signed-digit (SD) representation of the binary number in radix 2/sup k/, using digits -2/sup k-1/ to +2/sup k-1/ including 0. It is shown that a correct SD representation of the original number is obtained by scanning K+1-tuples (k>or=1) with one bit overlapping between adjacent groups. Recording of binary numbers has been used in computer arithmetic with 3-bit recoding being the dominant scheme. With the emergence of very high speed adders, hardware parallel multipliers using multibit recoding with k>2 are feasible, with the potential of improving both the performance and the hardware requirements. A parallel hardware multiplier based on the specific case of 5-bit recoding is proposed. Extensions beyond 5-bit recoding for multiplier design are studied for their performance and hardware requirements. Other issues relating to multiplier design, such as multiplication by a fixed or controlled coefficient, are also discussed in the light of multibit recoding.> Homayoon Sam, Arupratan Gupta |
IEEE Trans. Computers | 1 |