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Shu-Wei Wu

dblp:44/2244 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2000
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design
floorplanning
0.012000
B*-Trees: a new representation for non-slicing floorplans · DAC 2000
Electronic design automation › physical design › floorplanning
non-slicing floorplan representation
0.012000
B*-Trees: a new representation for non-slicing floorplans · DAC 2000
Electronic design automation
physical design
0.012000
B*-Trees: a new representation for non-slicing floorplans · DAC 2000

Methods — techniques the papers use, named apart from their topics

simulated annealing · 0.0
YearPublicationVenuePosition
2000 B*-Trees: a new representation for non-slicing floorplans
abstract
We present in this paper an efficient, flexible, and effective data structure, B*-trees for non-slicing floorplans. B*-trees are based on ordered binary trees and the admissible placement presented in [1]. Inheriting from the nice properties of ordered binary trees, B*-trees are very easy for implementation and can perform the respective primitive tree, operations search, insertion, and deletion in only O(1), O(1), and O(n) times while existing representations for non-slicing floorplans need at least O(n) time for each of these operations, where n is the number of modules. The correspondence between an admissible placement and its induced B*-tree is 1-to-1 (i.e., no redundancy); further, the transformation between them takes only linear time. Unlike other representations for non-slicing floorplans that need to construct constraint graphs for cost evaluation, in particular, the evaluation can be performed on B*-trees and their corresponding placements directly and incrementally. We further show the flexibility of B*-trees by exploring how to handle rotated, pre-placed, soft, and rectilinear modules. Experimental results on MCNC benchmarks show that the B*-tree representation runs about 4.5 times faster, consumes about 60% less memory, and results in smaller silicon area than the O-tree one [1]. We also develop a B*-tree based simulated annealing scheme for floorplan design; the scheme achieves near optimum area utilization even for rectilinear modules.
Yun-Chih Chang, Yao-Wen Chang, Guang-Ming Wu, Shu-Wei Wu
DAC4