This paper presents a novel approach for implementing Binary Neural Networks (BNNs) utilizing nonvolatile optical phase shifters. These phase shifters employ a micro-electromechanical system (MEMS) tuning mechanism, which enables the adjustment of the refractive index and phase of the propagating mode. In this approach, the weights of the BNN can be controlled by applying electrical signals to the phase shifters. Moreover, due to the nonvolatile operation of these devices, the network’s weights remain stable even when the electrical power source is cut off. The phases of the propagating modes, manipulated by the proposed phase shifters, determine the logic of the photonic circuit. The in-memory design of this device eliminates the need for network register banks, thereby significantly reducing resource usage, footprint, and power consumption. This approach offers much faster operation than other technologies, such as CMOS or spintronics, making it particularly appealing for edge artificial intelligence applications.

This article proposes a tunable true random number generator (TTRNG) based on stochastic magnetic tunnel junction (MTJ) switching in the subcritical current regime. The proposed design consists of three parts. The first part is a write/read circuit featuring a static write circuit and an energy-efficient circuit optimized for read operations. The second finds the probability generation array (PGA) similar to the longest common subsequence (LCS) problem. However, the algorithms presented so far for the LCS have not been responsive to finding the Desired-PGA as it must look for the common subsequence among one million sequences, each sequence being 259 long. Hence, the convergence of those algorithms is impossible in this problem. Accordingly, we propose an algorithm to find a common subsequence of length 24, each defining a logic function. We also propose a controller to generate arbitrary probabilities with a zero steady-state error. These parts, especially PGA, make the design highly robust to the process variations. Notably, the proposed design passes the National Institute of Standards and Technology test. The proposed design also reduces energy dissipation compared to previous designs. Also, as it does not require precise sizing, the FinFET technology is appropriately used to design the proposed approach.

Well-trained deep neural network (DNN) models are considered valuable assets because they require large amounts of data, expertise, and resources to achieve desired performance. Hence, protecting the intellectual property of such hard-to-develop models against unauthorized usage or model leaking is a significant concern. This paper proposes a novel key-based obfuscation method that locks the model with a significant accuracy drop when the incorrect key is applied. Due to the importance and developments of binary neural networks (BNNs) in hardware implementation of state-of-the-art DNN models, we study our method on BNNs. The proposed model protection solution leads to a higher accuracy drop with even a lower perturbation rate across different binary neural network architectures and benchmark datasets than its state-of-the-art counterpart. Furthermore, we present an efficient spintronic-based in-memory computing structure for the hardware implementation of the proposed method. We validate the proposed design using post-layout simulations based on the TSMC 40nm technology. With the same approach for hardware implementation, our proposed design provides, on average, 18%, 41%, and 40% improvements regarding the area, average power consumption, and weight modification energy per filter in the neural network structure, respectively.

In practical fuzzy applications, such as image processing, the utilization of precise models in hardware may not be the most efficient approach due to increased energy consumption and chip resource allocation. In a fuzzy system, an approximate implementation of min-max blocks offers an efficient solution with minimal accuracy compromise. Nevertheless, recent designs predominantly employ noncommercialized technologies for the fundamental fuzzy blocks. This article introduces a novel hardware solution for approximate fuzzy image edge detection using the well-established independent gate Fin field-effect transistor (FinFET) technology. The proposed hardware leverages two inference rules to identify edge pixels effectively. The fuzzy inference engine is implemented at the circuit level using 24 FinFETs, whereas the defuzzifier section incorporates four FinFETs with a configurable thresholding structure for optimal performance. Our circuit-level simulations reveal a remarkable 71% reduction in energy consumption compared with previous designs. The edge detection results are compared at the system level with the MATLAB Sobel edge detector. The proposed approximate hardware consistently matches the Sobel edge detection outcomes, exhibiting a 15% average improvements in data loss rate than other approximate structures. A figure of merit (FoM) is introduced to provide a comprehensive evaluation, considering both circuit and system-level metrics. The proposed FinFET-based hardware outperforms other approximate and even exact fuzzy edge detection hardware designs, boasting a 1.8 times higher FoM. This design paradigm exemplifies a promising direction toward compact and energy-efficient on-chip hardware implementations of real-world fuzzy systems.

In the above article[1], Fig. 5(b) belonged to another circuit (the Fe-CNTFET-based 2-transistor Schmitt trigger binary inverter, which is similar in the schematic to the circuit shown in Fig. 5 (a) of the above artice[1]but with different flat band voltages), which was inserted in the revised version of the article[1]by an unintentional mistake. The load line analysis of the circuit shown in Fig. 5 (a) of the article[1]is shown inFig. 1. For more clarity, the load line analysis has been plotted with more detail for Vin= 0.3V to 0.5V to indicate the performance of the ternary inverter in logic “1,” which matches the related VTC curve (Fig. 5 (c) shown in reference[1]).

Recently, integrating ferroelectric materials with nanotransistors such as carbon nanotube field-effect transistors (CNTFETs) has opened new doors for demonstrating a new generation of ultra-miniature circuits and systems. Utilizing the negative differential resistance effect in negative capacitance CNTFETs (NC-CNTFETs) has spurred the efforts for designing ultra-compact ternary circuits and systems similar to their binary structures. This paper presents an ultra-efficient ternary image edge detection hardware using NC-CNTFET technology. The proposed hardware is endowed with a noise reduction circuitry to mitigate the noise effects. Using four$1\times 3$kernels and concatenating the image pixels, the proposed ternary hardware has been designed using only 50 transistors. The proposed ternary hardware at the circuit level shows, on average, 74% improvements regarding power delay-product (PDP) compared to the CNTFET-based counterparts. Our comprehensive simulations indicate that the proposed NC-CNTFET-based hardware shows a 40% improvement in data loss, 2.2 times improvement in performance ratio, and 1.14 times improvement in Pratt’s figure-of-merit, respectively, compared to the related designs. Our results accentuate that the proposed NC-CNTFET-based ternary hardware is a breakthrough achievement in demonstrating ultra-efficient and noise-immune ternary image processing circuits beyond the conventional binary counterparts.

Multiple-valued logic (MVL) shows considerable advantages over binary logic in certain applications because of the increased informational content of its signals, and hence reduction in interconnects. Flip-flops (FFs) are the basic elements of many systems and are widely used in microprocessors due to their high performance. This article presents two spintronic ternary retention FFs, and a nonvolatile universal ternary shift register (NUTSR) based on gate-all-around carbon nanotube field-effect transistors (GAA-CNTFETs) and nonvolatile magnetic tunnel junction (MTJ). In the proposed input-aware ternary retention FF circuit, power consumption is significantly reduced by adding a magnitude comparator (MC) circuit and preventing duplicate data transfer to MTJs. Simulation results indicate that our design offers at least 22%, 40%, and 15% reductions in power consumption, backup time, and restore energy, respectively. Moreover, it eliminates the risk of data loss in the event of a sudden power outage.

In this paper, the impacts of the simultaneous switching noise (SSN) in carbon nanotube field effect transistor-based ternary circuits are investigated. These effects, including the peak noise on the VDD and ground rails and the SSN-induced delay and output noise are compared between traditional Cu and multiwall carbon nanotube bundle power interconnects in ternary circuits. Simulations are performed using HSPICE for global power interconnects at 14- and 7-nm technology nodes. The results indicate that for interconnects with 200 μm length, the peak SSN voltage on the VDD and ground rails for a power distribution network, including ten ternary buffers, using multi-walled carbon nanotube (MWCNT) bundle power interconnects is 53% and 40% lower, respectively, compared to Cu power interconnects in the last stage at the 14-nm node. Also, with scaling down the technology to 7 nm, these improvements increase to 60% and 59%, respectively. Moreover, MWCNT bundle power interconnects reduce the SSN-induced delay at the output of the tenth stage for interconnects with 200-μm length on average by 82% as compared to the Cu interconnects at the 14-nm node. This improvement is 73% for the 7-nm technology node.

To implement a fuzzy system, the first and the most essential step is to design basic fuzzy modules such as analog min and max circuits. This paper presents efficient minimum and maximum circuits using carbon nanotube FETs (CNTFETs) for nanotechnology-based fuzzy circuits and systems. The proposed approach considerably reduces the design complexity in the fuzzy space. In the proposed design, the chirality of carbon nanotubes is utilized for threshold voltage determination. Extensive simulations conducted using HSPICE and the Stanford CNTFET model at 16 nm feature size demonstrate that the proposed fuzzy logic blocks considerably improve the performance parameters and function much more robustly even in the presence of process variations, as compared to their CNTFET-based counterparts.

CMOS binary logic is limited by short channel effects, power density, and interconnection restrictions. The effective solution is non-silicon multiple-valued logic (MVL) computing. This study presents two high-performance quaternary full adder cells based on carbon nanotube field effect transistors (CNTFETs). The proposed designs use the unique properties of CNTFETs such as achieving a desired threshold voltage by adjusting the carbon nanotube diameters and having the same mobility as p-type and n-type devices. The proposed circuits were simulated under various test conditions using the Synopsys HSPICE simulator with the 32 nm Stanford comprehensive CNTFET model. The proposed designs have on average 32% lower delay, 68% average power, 83% energy consumption, and 77% static power compared to current state-of-the-art quaternary full adders. Simulation results indicated that the proposed designs are robust against process, voltage, and temperature variations, and are noise tolerant.

A Multi-stage Interconnection Network (MIN) is one of the choices for Networks-on-Chip (NoCs) architecture designer for its simple topology and easy scalability with low degree. The evolution of digital design lies in the ability to shrink circuit size with each advance in process technology. As CMOS implementing technology continues to scale down, standard interconnect will become a major bottleneck for on-chip MIN platform performance. One of the nanoelectronic architectures that have been reorganized as one of the top six emerging technologies in future computers, known as Carbon NanoTube (CNT). CNTs have emerged as a promising material for future generation ICs. It is our purpose, in this paper, to present a comparative performance study for implementation of six prominent MINs (i.e., Omega, Butterfly, Baseline, Generalized Cube, Benes, and Clos networks) using CNT-based switches. The performance measures studied are compared to that of conventional CMOS in 16nm process technology and reflect a great deal of improvement in the network performance.

Multi-stage Interconnection Networks (MINs) are important hardware platforms in various applications due to increasing design complexity and cost. Further, they are generally accepted concepts for solving the problems related to on-chip communications. Carbon nanotube (CNT) is a promising candidate for future on-chip interconnects and electro-thermal applications due to its superior electrical and thermal properties. Although MINs have been around for many years and they can greatly benefit as they reduce costs and complexities in the network, there has been hardly any attempt to exploit the CNT characteristics to design and implementation of MINs. In an attempt to fill this gap, this paper presents a novel method for implementation of MINs using CNT-based interconnects. The performance evaluation of these networks is compared to that of conventional CMOS interconnect in 16nm process technology and reflect a great deal of improvement in network performance.