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Kun-Jin Lin

dblp:44/3286 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 2000
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 50% Integrated circuit design · 17% Memory systems · 17%

Topics — the 6 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › domain-specific accelerator
compression accelerator
0.012000
A Low-Power CAM Design for LZ Data Compression · IEEE Trans. Computers 2000
Memory systems
content-addressable memory
0.012000
A Low-Power CAM Design for LZ Data Compression · IEEE Trans. Computers 2000
Electronic design automation › hardware verification and test › fault modeling
functional fault model
0.012000
Testing content-addressable memories using functional fault modelsand march-like algorithms · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000
Electronic design automation
hardware verification and test
0.012000
Testing content-addressable memories using functional fault modelsand march-like algorithms · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000
Integrated circuit design
low-power circuit design
0.012000
A Low-Power CAM Design for LZ Data Compression · IEEE Trans. Computers 2000
Electronic design automation › hardware verification and test
memory testing
0.012000
Testing content-addressable memories using functional fault modelsand march-like algorithms · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000

Methods — techniques the papers use, named apart from their topics

march-like algorithms · 0.0functional fault modeling · 0.0
YearPublicationVenuePosition
2000 A Low-Power CAM Design for LZ Data Compression
abstract
Low-power and high-performance data compressors play an increasingly important role in the portable mobile computing and wireless communication markets. Among lossless data compression algorithms for hardware implementation, LZ77 is one of the most widely used. For real-time communication, some hardware LZ compressors/decompressors have been proposed in the past. Content addressable memory (CAM) is widely considered as the most efficient architecture for pattern matching required by the LZ77 compression process. In this paper, we propose a low-power CAM-based LZ77 data compressor. By shutting down the power for unnecessary comparisons between the CAM words and the input symbol, the proposed CAM architecture consumes much lower power than the conventional ones without noticeable performance penalty. Moreover, using the proposed conditional comparison mechanism and the novel CAM cell with the NAND-type matching logic, on average we have close to two orders of improvement on power consumption, i.e., a reduction of more than 98 percent for 8-bit words. Speed is sacrificed if we use the NAND-type matching logic, but the NAND-type logic and the NOR-type logic can be combined to provide the best solution that balances power and delay. Our approach also can be applied to general-purpose CAMs which use the valid bits, so far as the proposed design techniques are adopted.
Kun-Jin Lin, Cheng-Wen Wu
IEEE Trans. Computers1
2000 Testing content-addressable memories using functional fault modelsand march-like algorithms
abstract
Functional tests for content-addressable memories (CAM's) are presented in this paper. In addition to several traditional functional fault models for RAM's, we also consider the fault models based on physical defects, such as shorts between two circuit nodes and transistor stuck-on and stuck open faults. Accordingly, several functional fault models are proposed. In order to make our approach suited to various application-specific CAM's, we propose tests which require only three fundamental types of operation (i.e., write, erase, and compare), and the test results can be observed entirely from the single-bit Hit output. A complete, compact test is also proposed, which has low complexity and is suitable for modern high-density and large-capacity CAMs-it requires only 2N+3w+2 compare operations and 8N write operations to cover the functional fault models discussed, where N is the number of words and w is the word length.
Kun-Jin Lin, Cheng-Wen Wu
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1