Illumination changes present challenging problems to video surveillance algorithms tasked with identifying and tracking objects. Illumination changes can drastically alter the appearance of a scene, causing truly salient features to be lost amid otherwise stable background. We describe an illumination change compensation method that identifies large, stable, chromatically distinct background features-called BigBackground regions - which are used as calibration anchors for scene correction. The benefits of this method are demonstrated for a computationally low-cost kinematic tracking application as it attempts to track objects during illumination changes. The BigBackground-based method is compared with other compensation techniques, and is found to successfully track 60% to 80% more objects during illumination changes. Video sequences of pedestrian and vehicular traffic are used for evaluation.

Advances in semiconductor technology enable larger processor design space, leading to increasingly complex systems. Designers must evaluate many architecture design points to achieve the optimal design. Currently, most architecture exploration is performed using cycle accurate simulators. Although accurate, these tools are slow, thus limiting a comprehensive design search. The vast design space of today's complex processors and time to market economic pressures motivate the need for faster architectural evaluation methods. This paper presents a superscalar processor performance model that enables rapid exploration of the architecture design space for superscalar processors. It supplements current design tools by quickly identifying promising areas for more thorough and time consuming exploration with traditional tools. The model estimates instruction throughput of a superscalar processor based on early architectural design parameters and application properties. It has been validated with the Simplescalar out-of-order simulator. The model, which executed 40,000 times faster, produces instruction throughput estimates that are with within 5.5% of the corresponding SimpleScalar values.

Traditional video scene analysis depends on accurate background modeling to identify salient foreground objects. However, in many important surveillance applications, saliency is defined by the appearance of a new non-ephemeral object that is between the foreground and background. This midground realm is defined by a temporal window following the object's appearance; but it also depends on adaptive background modeling to allow detection with scene variations (e.g., occlusion, small illumination changes). The human visual system is ill-suited for midground detection. For example, when surveying a busy airline terminal, it is difficult (but important) to detect an unattended bag which appears in the scene. This paper introduces a midground detection technique which emphasizes computational and storage efficiency. The approach uses a new adaptive, pixel-level modeling technique derived from existing backgrounding methods. Experimental results demonstrate that this technique can accurately and efficiently identify midground objects in real-world scenes, including PETS2006 and AVSS2007 challenge datasets.

Automated video surveillance applications require accurate separation of foreground and background image content. Cost sensitive embedded platforms place realtime performance and efficiency demands on techniques to accomplish this task. In this paper we evaluate pixel-level foreground extraction techniques for a low cost integrated surveillance system. We introduce a new adaptive technique, multimodal mean (MM), which balances accuracy, performance, and efficiency to meet embedded system requirements. Our evaluation compares several pixel-level foreground extraction techniques in terms of their computation and storage requirements, and functional accuracy for three representative video sequences. The proposed MM algorithm delivers comparable accuracy of the best alternative (Mixture of Gaussians) with a 6X improvement in execution time and an 18% reduction in required storage.

Modern embedded processors are designed to maximize execution efficiency—the amount of performance achieved per unit of energy dissipated while meeting minimum performance levels. To increase this efficiency, we propose utilizing static strands , dependence chains without fan-out, which are exposed by a compiler pass. These dependent instructions are resequenced to be sequential and annotated to communicate their location to the hardware. Importantly, this modified application is binary compatible and functionally identical to the original, allowing transparent execution on a baseline processor. However, these static strands can be easily collapsed and optimized by simple processor modifications, significantly reducing the workload energy. Results show that over 30% of MediaBench and Spec2000int dynamic instructions can be collapsed, reducing issue logic energy by 20%, bypass energy 19%, and register file energy 14%. In addition, by increasing the effective capactity of pipeline resources by almost a third, average IPC can be improved up to 15%. This performance gain can then be traded in for a lower clock frequency to maintain a basline level of performance, further reducing energy.

All optical path interconnection networks employing dense wavelength division multiplexing can provide vast improvements in supercomputer performance. However, the lack of efficient optical buffering requires investigation of new topologies and routing techniques. This paper introduces and evaluates the data vortex optical switching architecture which uses cylindrical routing paths as a packet buffering alternative. In addition, the impact of the number of angles on the overall network performance is studied through simulation. Using optimal topology configurations, the data vortex is compared to two existing switching architectures-butterfly and omega networks. The three networks are compared in terms of throughput, accepted traffic ratio, and average packet latency. The data vortex is shown to exhibit comparable latency and a higher acceptance rate (2times at 50 percent load) than the butterfly and omega topologies

For multimedia processing, modern instruction-level parallel (ILP) processors are faced with limited parallelism and inevitable communication issues, as silicon feature size decreases and pipelines become wider. In this paper, we propose and evaluate a dynamic optimization mechanism that exploits regular operand distribution patterns in multimedia applications. The proposed methodology i) improves performance by recognizing and extracting more parallelism than conventional ILP processors; ii) lowers the burden of operand transport by localizing the communication between instructions based on the operand characteristics; and iii) maintains binary compatibility by applying run-time optimization rather than requiring changes to the ISA, recompilation with a vectorizing compiler, or manual retargeting and optimization

This paper presents an efficient two-stage filtering method that provides highly reliable 4:2:0 YCbCr signals, which are widely used in the image- and video-processing community. In the first phase, we use an index mapping, center-weighted median filter (IMCWMF) to detect and remove noise from luminance (Y) components while inheriting the chrominance components (Cb and Cr) for the selected median luminance. In the second phase, we use a downsampling sigma filter (DSF) to detect and remove noise from the chrominance components while performing the downsampling process. Simulation results indicate that the proposed method outperforms other nonlinear filters in terms of both noise attenuation and signal-detail preservation while providing accurate color channel information for the JPEG compression process and overall image quality.

As technology trends yield shorter cycle times and larger, wider datapaths in architectures for multimedia systems, global broadcast networks for operand communication are becoming a major bottleneck in processor performance. New low latency operand transport techniques are needed. This paper proposes and evaluates lower cost mechanisms than traditional bypass networks, exploiting regular operand distribution patterns in multimedia applications. To reduce latency associated with operand movement within a datapath, our mechanism, called dynamic instruction clustering, groups chains of dependent instructions within a basic block at runtime, identifies intermediate value transportation, and schedules it on networked ALUs which are connected by a local dedicated network. By converting global communication into local, the transport latency can be minimized and the critical path of the application code can be executed in consecutive, shortened cycles, resulting in improved performance. We demonstrated that 28% and 30% of total dependence edges residing in the instruction window can be localized on 8 and 16-way machines, respectively. Our results show that the overall performance gains over a wide range of multimedia applications are 16% for 8-way and 35% for 16-way on average.

Modern embedded processors are designed to maximize execution efficiency--the amount of performance achieved per unit of energy dissipated while meeting minimum performance levels. To increase this efficiency we propose utilizing static strands, dependence chains without fan-out which are exposed by a compiler pass. These dependent instructions are resequenced to be sequential and annotated to communicate their location to the hardware. Importantly, this modified application is binary compatible and functionally identical to the original, allowing transparent execution on a baseline processor. However, these static strands can be easily collapsed and optimized by simple processor modifications, significantly reducing the workload energy. Results show that over 30% of MediaBench and Spec2000int dynamic instructions can be collapsed, reducing issue logic energy by 16 to 24%, bypass energy 17 to 20%, and register file energy 13 to 14%. Additionally, by increasing the effective capactity of pipeline resources by almost a third, average IPC can be improved up to 15%. This performance gain can then be traded in for a lower clock frequency to maintain a basline level of performance, reducing energy further.

Atlas, a dynamically multithreading chip-multiprocessor (CMP), gains little complexity as processing elements are added. When the model is scaled up with strategic layouts and realistic latencies, area and power efficiency surpass that of an aggressive out-of-order processor, though results are sensitive to global communication delay.

In the modern era of wire-dominated architectures, specific effort must be made to reduce needless communication within out-of-order pipelines while still maintaining binary compatibility. To ease pressure on highly-connected elements such as the issue logic and bypass network, we propose the dynamic detection and speculative execution of instruction strands-linear chains of dependent instructions without intermediate fan-out. The hardware required for detecting these chains is simple and resides off the critical path of the pipeline, and the execution targets are the normal ALUs with a self-bypass mode. By collapsing these strings of dependencies into atomic macro-instructions, the efficiency of the issue queue and reorder buffer can be increased. Our results show that over 25% of all dynamic ALU instructions can be grouped, decreasing both the average reorder buffer occupancy and issue queue occupancy by over a third. Additionally, these strands have several properties which make them amenable to simple performance optimizations. Our experiments show average IPC increases of 17% on a four-wide machine and 20% on an eight-wide machine in Spec2000int and Mediabench applications. Finally, strands ease the IPC penalties of multicycle issue and bypass by reducing dependency pressures, providing opportunity for clock frequency gains as well.

As inexpensive imaging chips and wireless telecommunications are incorporated into an increasing array, of portable products, the need for high efficiency, high throughput embedded processing will become an important challenge in computer architecture. Videocentric applications, such wireless videoconferencing, real-time video enhancement and analysis, and new, immersive modes of distance education, will exceed the computational capabilities of current microprocessor and digital signal processor (DSP) architectures. A new class of embedded computers, portable video supercomputers, will combine supercomputer performance with the energy efficiency required for deployment in portable systems. We examine one candidate portable video supercomputer, a low memory, monolithically integrated SIMD architecture (SIMPil) that exploits the substantial data parallelism that exists in a suite of implemented video processing applications. The processing element microarchitecture is optimized using a novel technique that combines application simulation and technology modeling to provide a desired combination of performance, area, and energy consumption. Analysis results show that, for MPEG encoding, a SIMPil array implemented in 100 nm CMOS provides 100x greater performance and 10x higher energy efficiency than today's DSPs implemented 150 nm CMOS. This is accomplished using execution parallelism and a carefully selected processing element design. This research demonstrates that appropriately designed SIMD arrays, implemented monolithically in today's technology, can provide high performance and high efficiency for embedded video processing.

A critical problem in wide-issue superscalar processors is the limit on cycle time imposed by the central register file and operand bypass network. Here, a distributed register file architecture that employs fully distributed functional unit clusters is presented. It utilizes a local register mapping table and a dedicated register transfer network to support distributed register operations. In addition, an eager transfer mechanism is developed to reduce penalties caused by incomplete operand transport interconnection. Distributed register files can be employed to reduce operand access time by a factor of two with associated average IPC penalties of 14% and 21% on 4- and 8-way superscalar architectures across a broad range of symbolic, scientific, and multimedia applications. The IPC penalties are only 3% and 10% for SpecINT2000 applications.

This paper presents quantized color pack eXtension (QCPX) ISA to accelerate performance of pixel-oriented media processing applications. The QCPX ISA (with a 32 bit word size) supports two packed, quantized (reduced) 16-bit color pixels represented in a YCbCr (Y: luminance, Cr and Cb: chrominance) color format. Unlike typical multimedia instruction set extensions (e.g., MDMX, MMX, ALTIVEC), QCPX obtains substantial performance and code density improvements through implicit support for color pixel processing rather than depending solely on generic subword parallelism. To fully measure its impact, QCPX is evaluated in the context of a massively data-parallel SIMD execution platform where data parallelism is harnessed by an orthogonal mechanism. Simulation results indicate that the 32-bit QCPX ISA achieves an overall average speedup of 584% over the non-QCPX and 88% over the 32-bit MDMX-like ISA with four media applications in a same machine platform. In addition, QCPX results in a higher system utilization in excess of 95% due to a significant reduction of conditional instructions.

The growing speed gap between transistors and wire interconnects is forcing the development of distributed, or clustered, architectures. These designs partition the chip into small regions with fast intracluster communication. Longer latency is required to communicate between clusters. The hardware and/or software are responsible for scheduling instructions to clusters such that critical path communication occurs within a cluster. This paper presents GENEric SYstems Simulator (GENESYS), a technology modeling tool that captures a broad range of materials, device, circuit, and interconnect parameters across current and future semiconductor technology. This tool is used to explore the relationship between key technology parameters (intercluster wire delay and transistor switching delay) and key architecture parameters (superscalar versus multithreaded instruction dispatch, and value prediction support). GENESYS is used to predict intercluster latencies as VLSI technology advances. The study provides quantitative data showing how conventional superscalar performance is degraded with increasing wire latency. Threaded designs are more tolerant to wire delay. Optimal thread size changes with advancing VLSI technology, suggesting a highly adaptive architecture. Value prediction is shown to be useful in all cases, but provides more benefit to the multithreaded design.

Portable image processing applications require an efficient, scalable platform with localized computing regions. This paper presents a new class of area I/O systolic architecture to exploit the physical data locality of planar data streams by processing data where it falls. A synthesis technique using dependence graphs, data partitioning, and computation mapping is developed to handle planar data streams and to systematically design arrays with area I/O. Simulation results show that the use of area I/O provides a 16 times speedup over systems with perimeter I/O. Performance comparisons for a set of signal processing algorithms show that systolic arrays that consider planar data streams in the design process are up to three times faster than traditional arrays.

Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communicate at significantly higher speeds while operating more efficiently to meet system size, weight, power, and energy requirements. As high-performance parallel computing architectures make their way into portable systems, compact, efficient, and error-tolerant computing and communication mechanisms will be required. This paper presents the High-Performance Efficient Router (HiPER), an efficient multidimensional router supporting high-throughput error-corrected communication channels. HiPER is a proof-of-concept vehicle for efficient implementations of routing, switching, and error control mechanisms. It combines mad postman (bit-pipelined) switching with dimension-order routing, producing a low-latency routing router that is less sensitive to message distance than a word parallel crossbar router. To maintain robust communication as link speeds increase and link power budgets decrease, HiPER employs flit-level hop-by-hop retransmission of erroneous flits, which provides builtin error control at the network level. Data presented on the implemented bit serial version of HiPER offer insight into future router designs with channel sizes between bit-serial and word-wide.

Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular technique to counter this issue involves the usage of decoupling capacitors. This paper presents a novel design technique for sizing and placing on-chip decoupling capacitors based on activity signatures from the microarchitecture. Simulation of a typical processor workload (SPEC95) provides a realistic stimulation of microarchitecture elements that is coupled with a spatial power grid model. Evaluation of the proposed technique on typical microprocessor implementations (the Alpha 21264 and the Pentium II) indicates that this technique can produce up to a 30% improvement in maximum noise levels over a uniform decoupling capacitor placement strategy.

Single-chip multiprocessors are an important research direction for future microprocessors. The stigma of this approach is that many important applications cannot be automatically parallelized. This paper presents a single-chip multiprocessor that engages aggressive speculation techniques to enable dynamic parallelization of irregular, sequential binaries. Thread speculation and data value prediction are combined to enable the processor to execute dependent threads in parallel. The architecture performs a novel form of dynamic thread partitioning and includes an aggressive correlated value predictor. Microarchitectural structures manage interthread data and control dependencies. On an eight processor system, simulated execution of SPECint95 binaries delivers a speedup of 3.4 over a scalar in-order uniprocessor. This improvement is due entirely to the exploitation of dynamically extracted thread level parallelism.

On-chip interconnect demand is becoming the dominant factor in modern processor performance and must be estimated early in the design process. This paper presents a set of heterogeneous architectural models that combines architecture description and Rent's rule-based wiring models. These architecture models allow flexible heterogeneous system specifications, enabling investigations of prospective designs in different technology scenarios. Comparisons against actual data demonstrate the models' effectiveness for architecture explorations with highly accurate estimations of local and global wiring demand, as well as chip area and cycle time. Simulation of two candidate system designs reveal trends in interconnect delay with increasing architectural complexity, and confirm the need for high computational locality and short global wires for future architectures.

An important research direction for future microprocessors is the single-chip multiprocessor. The drawbacks of this approach are that many important applications cannot be automatically parallelized and that performance suffers with "dusty-deck" binaries. This paper details a single-chip multiprocessor that engages a combination of aggressive speculation techniques to enable the dynamic parallelization of irregular, sequential binaries. Thread speculation (multiscalar execution) and data value prediction are combined to enable the processor to execute dependent threads in parallel. The architecture performs a novel form of dynamic thread partitioning called MEM-slicing, and includes an extremely aggressive correlated value predictor. Several new microarchitectural structures to manage inter-thread dependencies are described. Simulations show that sequential programs are amenable to this form of execution. Over SPECint95, an average speedup of 3.4 is achieved on 8 processors due entirely to the exploitation of thread level parallelism.

Article An architectural solution for the inductive noise problem due to clock-gating Share on Authors: Mondira Deb Pant Georgia Institute of Technology, Atlanta, GA Georgia Institute of Technology, Atlanta, GAView Profile , Pankaj Pant View Profile , D. Scott Wills Georgia Institute of Technology, Atlanta, GA Georgia Institute of Technology, Atlanta, GAView Profile , Vivek Tiwari Intel Corporation, Santa Clara, CA Intel Corporation, Santa Clara, CAView Profile Authors Info & Claims ISLPED '99: Proceedings of the 1999 international symposium on Low power electronics and designAugust 1999 Pages 255–257https://doi.org/10.1145/313817.313938Online:17 August 1999Publication History 42citation309DownloadsMetricsTotal Citations42Total Downloads309Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Thread level speculative execution, together with value prediction to break data dependencies between threads, may enable efficient single program execution on a closely coupled chip multiprocessor. This paper describes a method to partition sequential programs such that a minimum number of hard-to-predict data dependencies cross thread boundaries. SPEC95 binaries are partitioned and then executed on an idealized simulator in order to study the limits of this technique. Value prediction is shown to be crucial to exposing thread level parallelism (TLP). Simple value predictors promise modest to large gains if thread boundaries are properly identified. Concurrent execution of fully data independent threads on 8 processors gives a geometric mean speedup of 2.4 for the benchmarks studied.

Three-dimensional packaging technologies are critical for enabling ultra-compact, massively parallel processors (MPPs) for embedded applications. Through-water optical interconnect has been proposed as a useful technology for building ultra-compact MPPs since it provides a simplified mechanism for interconnecting stacked multichip substrates. This paper presents the offset cube, a new network topology designed to exploit the packaging benefits of through-wafer optical interconnect in ultra-compact MPP systems. We validate the offset cube's topological efficiency by developing deadlock-free adaptive routing protocols with modest virtual channel requirements (only two virtual channels per link needed for full adaptivity). A preliminary analysis of router complexity suggests these protocols can be efficiently implemented in hardware. We also present a 3D mesh embedding for the offset cube. Network simulations show the offset cube performs comparably to a bidirectional 3D mesh of equal size under uniform, hot-spot, and trace-driven traffic loads. While the offset cube is not proposed as a general replacement for the mesh topology it leverages the benefits of through-wafer optical interconnect more effectively than a mesh by completely eliminating chip-to-chip wires for data signals. Hence, the offset cube is an effective topology for interconnecting ultra-compact MCM-level MPP systems.

This paper describes Pica, a fine-grain, message-passing architecture designed to efficiently support high-throughput, low-memory parallel applications, such as image processing, object recognition, and data compression. By specializing the processor and reducing local memory (4,096 36-bit words), multiple nodes can be implemented on a single chip. This allows high-performance systems for high-throughput applications to be realized at lower cost. The architecture minimizes overhead for basic parallel operations. An operand-addressed context cache and round-robin task manager support fast task swapping. Fixed-sized activation contexts simplify storage management. Word-tag synchronization bits provide low-cost synchronization. Several applications have been developed for this architecture, including thermal relaxation, matrix multiplication, JPEG image compression, and Positron Emission Tomography image reconstruction. These applications have been executed using an instrumented instruction-level simulator. The results of these experiments and an evaluation of Pica's architectural features are presented.

Abstract only given. A significant amount of current research on vector quantization (VQ) implementations addresses increasing the speed of image encoding. This is typically accomplished by imposing structures, exploiting properties of the distance measure, or developing efficient and fast implementations. This research proposes a parallel implementation of a full-search VQ encoding algorithm using a low memory, fine grain SIMD pixel processor (SIMPil) being developed at Georgia Tech. This implementation fully exposes the available parallelism of the encoding process and exploits the processing and I/O capabilities of the processor, resulting in a system that can perform real-time image and video compression. The proposed implementation encodes a large region of the original image at once, replacing each constituent input block with its corresponding VQ codeword index. Preliminary simulation results indicate that the proposed implementation is capable of sustain real-time frame rates. In the simulation, 92058 clock cycles are required to encode a single 64/spl times/64 region. The image of Lena (256/spl times/256) requires 16 passes to be completely encoded, for a total of about 1472089 clock cycles. With a 50 MHz processor, a 256/spl times/256 image frame will be encoded in 29.4 ms, supporting a frame rate of >30 frames/sec. Three VQ implementations are compared on different hardware platforms. A prototype SIMPil implementation is being fabricated by MOSIS in 0.8 /spl mu/m CMOS.

The rapid advance of VLSI and packaging technologies has a significant impact on system architecture. In this paper, an analytical model is used to explore the design space of interconnection networks for a 4,096 node processing system incorporating multi-node chips packaged on a single MCM substrate. Possible designs are evaluated for a two-level interconnect with separate k-ary n-cube networks for intrachip and interchip communication. An analysis of the impact several architectural and technological parameters have on the optimal network implementation (based on average no-load latency) is presented.

Recent architectural and technological advances have led to the feasibility of a new class of massively parallel processing systems based on a fine-grain, message-passing computational model. These machines provide a new alternative for the development of fast, cost-efficient Maximum Likelihood-Expectation Maximization (ML-EM) algorithmic formulations. As an important first step in determining the potential performance benefits to be gathered from such formulations, we have developed an ML-EM algorithm suitable for the high-communications, low-memory (HCLM) execution model supported by this new class of machines. Evaluation of this algorithm indicates a normalized least-square error comparable to, or better than, that obtained via a sequential ray-driven ML-EM formulation and an effective speedup in execution time (as determined via discrete-event simulation of the Pica multiprocessor system currently under development at the Georgia Institute of Technology) of well over two orders of magnitude compared to current ray-driven sequential ML-EM formulations on high-end workstations. Thus, the HCLM algorithmic formulation may provide ML-EM reconstructions within clinical time-frames.

Introduces Pica, a fine-grain, message-passing architecture designed to efficiently support high-throughput parallel applications. The architecture minimizes overhead for basic parallel operations. An operand-addressed context cache and round-robin task manager allow single-cycle task swaps. Fixed-sized activation contexts simplify storage management. Word-tag synchronization bits provide low-cost synchronization. The focus on high-throughput applications allows a small local memory (1024 36-bit words). A complete node (including memory) can be implemented using a fraction of a chip. A multi-node chip prototype (four nodes/chip) is being designed. In order to meet chip I/O requirements, a high-bandwidth 3D optical network is also being designed. Using recent developments in epitaxial liftoff of optoelectronic devices and through-chip transmission, a network is presented that provides 3.2 Gbit/s off-chip bandwidth.>

This paper introduces a scalable inter connection network based on integrated optical devices developed at Georgia Tech. It incorporates arrays of optical transmitters and detectors placed on top of sil icon chips which are then arranged on a silicon sub strate. Staggering these substrates to overlap chips in different planes forms an offset cube topology. This paper examines this novel optoelectric communication network. It explains the physical network architecture and the offset cube topology, and summarizes its per formance. Combining this optoelectronic communica tion network with new fine-grain machine architectures (multi-node per chip) can lead to extremely dense, high performance parallel systems

A description is given of the Message-Driven Processor (MDP), an integrated multicomputer node. It incorporates a 36-bit integer processor, a memory management unit, a router for a 3D mesh network, a network interface, a 4K*36-bit word static RAM (SRAM), and an ECC dynamic RAM (DRAM) controller on a single 1.1 M-transistor VLSI chip. The MDP is not specialized for a single model of computation. Instead, it incorporates efficient primitive mechanisms for communication, synchronization, and naming. These mechanisms support most proposed parallel programming models. Each processing node of the MIT J-Machine consists of an MDP with 1 Mbit of DRAM.>

The static data-flow model of computation promises high-performance from fine-grained parallelism, but conventional token-driven static data-flow architectures are inefficient in terms of memory bandwidth and microcycles required per operation. The associative template mechanism, an application of associative techniques, uses specially configured content-addressable memories to provide efficient flow control for static data-flow program execution. It supports static data-flow semantics while exhibiting memory bandwidth and microcycle demands comparable to those of conventional uniprocessors. Associative diffusion, a second application of associative methods, provides a communication between adjacent nodes of a mesh-connected network of associative-template-based processors. This mechanism achieves nearest-neighbor communication at speeds comparable to intranode transactions by overlapping domains of associativity across boundaries between neighboring nodes. Together, associative templates and associative diffusion provide a token-free approach to static data-flow computation.>

We propose a machine architecture for a high-performance processing node for a message-passing, MIMD concurrent computer. The principal mechanisms for attaining this goal are the direct execution and buffering of messages and a memory-based architecture that permits very fast context switches. Our architecture also includes a novel memory organization that permits both indexed and associative accesses and that incorporates an instruction buffer and message queue. Simulation results suggest that this architecture reduces message reception overhead by more than an order of magnitude.