The desire for large size, high-speed, and low-power on-chip memory necessitates early and accurate estimates of memory performance. A new performance model as well as an early cache design tool and predictor of access and cycle time for cache stack (PRACTICS) has been developed for on-chip static random access memory (SRAM) cache design that includes both delay and dynamic-power models. Efficient models for distributed interconnect delays, verified by Cadence simulations, are introduced, and their necessity is demonstrated. In the delay model, the access time is estimated by decomposing each component into several equivalent lumped resistance-capacitance (RC) circuits and using an appropriate order pi model to approximate the distributed wire delays of each stage. The dynamic-power model calculates the charging power dissipation of the load capacitances using the same equivalent lumped RC circuits. The delay model has been validated with an Intel 18-Mb SRAM at the 180-nm node, achieving accuracy to within 10% of the measured results. The dynamic-power model has been validated with an International Business Machines Corporation (IBM) 18-Mb SRAM at the 180-nm node, to within 13% of the measured power consumption. Detailed comparisons between PRACTICS and cache access and cycle time model (CACTI) in both validation cases indicate that an improved wire delay, appropriate circuit structures, and technology dependent parameters are necessary to accurately predict large cache memory performance at deep submicrometer technology nodes. PRACTICS is used to analyze the access time and power consumption in terms of cache sizes and various degrees of associativity for architectural studies. In addition, the PRACTICS simulation results show that repeater insertion reduces the access time significantly, with a small overhead in dynamic-power consumption for large size cache design at deep submicrometer technology

A cache access time model, PRACTICS (predictor of access and cycle time for cache stack), has been developed to optimize the memory array architecture for the minimum access and cycle times of on-chip memory using circuit models based on Cadence simulations. Lumped RC models have been used to approximate the distributed RC interconnect network in the access time models. Both SRAM and DRAM models have been validated with industrial designs. The limited influences of gate far-out and transistor size on the cache array architecture indicate that interconnect delay is dominant at deep submicron technologies.