This paper presents a 1stOrder Quasi-Passive Sigma-Delta Modulator developed in 65 nm technology which fits in a 30 × 36 µm2area, for applications in Organ-on-Chip systems. In these systems, low power dissipation is crucial to avoid heating biological parts and to maintain a stable temperature. It is also desirable to have ultra-compact analog-to-digital converters so the signals from a single cell or a single sensor of a large sensor matrix can be individually conditioned. This circuit fills a gap in low to medium-frequency efficient compact analog-to-digital converter literature. The circuit achieves an area smaller than 1080 µm2and power consumption lower than 10 µW while having an SNDR of 51.1 dB, and thus, an ENOB of 8.2 bit, as well as a bandwidth of over 50 kHz.

This paper describes a course offered in the Master program in Electrical and Computer Engineering of Instituto Superior Tecnico, Universidade de Lisboa, and offered within the GreenChips-EDU platform. The course is on Ultra Low Power Circuits design. The novelty of this course is that the emphasis is on design of analog and digital circuits with CMOS technology using the transistors in subthreshold region, and less conventional low power topologies for RF circuits. The course uses professional CAD tools, currently "Cadence Design Framework II", and on production materials for the use of "Synopsys Custom Compiler", configured with a foundry technology design kit with precise modelling in all regions of operation of a MOS transistor. The design flow procedure is in accordance with common practices used in the industry. The proposed model has been classroom tested in the last three years with positive student reviews on course quality assessment.

Ring oscillators are widely used in modern applications due to their simplicity, compact size, and low power consumption. Their oscillation frequency is determined by the number of stages (or inverters) and the average delay per inverter. In advanced submicron technologies, logic gates’ minimal propagation delay allows high-frequency operation with great efficiency. However, ring oscillators become increasingly power-inefficient at lower frequencies (MHz range). This paper presents a novel oscillator topology that combines two injection locked stacked ring oscillators with different stage counts, generating two output frequencies with a fractional ratio. The stacking technique reuses the supply current while splitting the available supply voltage across the two oscillators. This approach effectively reduces the oscillation frequency while maintaining energy efficiency and improving phase noise performance by approximately 3 dBc/Hz across all frequencies. Simulation results in TSMC 65nm confirm that the locking mechanism of two stacked ring oscillators is achieved, even when they contain different numbers of inverters, enabling fractional injection locking.

Advances in bioelectronic medicine have led to a reduction in implant size and notable improvements in energy management and data transmission techniques. Bulky titanium casings traditionally used to shield implant electronics are being gradually replaced by more streamlined materials, primarily composed of polymers and thin film ceramics. This transition offers numerous advantages, including a smaller form factor, enhanced flexibility, and the facilitation of wireless power and data transmission. However, it is essential to acknowledge potential drawbacks of these innovative encapsulation materials, such as the unknown longevity and adhesion issues that may compromise hermeticity. To investigate the hermeticity and long-term performance of conformal encapsulations, we propose a fully encapsulated wireless monitoring system with novel circuitry. The system comprises energy harvesting, humidity assessment, and passive communication. In this paper, we delve into each of these areas, presenting innovative solutions that are later implemented and tested. The final system is realized in an integrated circuit technology of 65 nm, fitting in a compact area of 0.3 mm2 ($76~\%$occupied by the integrated receiver coil), while consuming$1.3~\mu $W. All the necessary components are fully integrated, allowing for increased miniaturization and lower power consumption.

Cardiovascular diseases are one of the major causes of death worldwide, which drives the research on smart catheters for early diagnosis. Deploying ASICs at the tip of the catheter is challenging, as power is delivered through a long and thin wire, limiting the power integrity. Also, since the catheter needs to fit into the diameter of a blood vessel or other narrow channel in the human body, there is no room for bulky decoupling capacitors. Finally, power consumption must be optimized, as the energy density may lead to prohibitive heating of tissues and fluids. Still, while targeting better performance, e.g. higher imaging resolution, the requirements for bandwidth and accuracy consistently increase, ultimately demanding precise on-chip clock generation for communication and digitization. In this paper we propose a circuit for at-the-tip clock generation in smart catheters, comprising a low-drop out (LDO) regulator, voltage and current references and a low-jitter digitally controlled oscillator (DCO). The clock generator also comprises a clock divider with programmable duty cycle, allowing system reconfiguration. The circuit is laid out and simulated under application conditions. The LDO achieves a full-spectrum power supply ripple rejection (PSRR) of 50 dB with an output load of 10 mA. The DCO, supplied by the aforementioned LDO, achieves a phase noise of -104.5 dBc/Hz at an offset of 1 MHz and 1.25 GHz of oscillating frequency. The proposed clock generator allows digitization at 200 MSps with a maximum SNR of 56.3 dB for an input signal of 50 MHz if phase noise is integrated from 100 kHz to 625 MHz.

Ring oscillators are one of the simplest, smallest and most energy-efficient topologies when it comes to clock generation. Being implemented using a chain of digital inverters, their oscillation frequency can be set by the inverters count in the chain and the delay of each inverter. This is an advantage when considering the simplicity and size, however, it is also the cause for high frequency variation with temperature. In this paper we propose an ultra-low power oscillator circuit that exploits a stack of small ring oscillators for supply current reuse and injection locking, which provides phase noise improvement. Frequency stability is achieved through a feedback loop that relies on a frequency-to-voltage converter with improved linearity and reduced temperature sensitivity based on MOS capacitors. Simulation results show that the oscillation frequency changes ±0.4% from 0 to 70°C (57 ppm/°C) while consuming 2.4 μW at 10 MHz, with a phase noise of -88.9 dBc/Hz at 100 kHz offset.

The ring oscillator is the topology of choice in many modern applications given its simplicity, small area footprint, low-power and ability of being implemented with digital inverters. The oscillation frequency is dictated by the number of stages in the chain and the average delay of the inverters. In deep submicron processes, the very short propagation delay of logic gates makes the ring oscillator a very energy-efficient solution for high frequencies of operation, whereas for low frequencies the efficiency generally drops because larger capacitances must be driven to slow down the transitions. In this paper we propose a topology of oscillator that employs four injection-locked stacked ring oscillators, reusing current while the available supply potential is divided among these stages, naturally reducing the oscillation frequency while maintaining energy efficiency. The output signal is recovered to the supply rails through a level shifter circuit with feedback, allowing to adjust its threshold to deal with PVT variations. Simulation results show that the circuit operates from 3-10 MHz, while consuming 0.7 μW at 10 MHz, with a phase noise of -88.8 dBc/Hz at 100 kHz offset, leading to a FoM of -160 dB.

Injection locking of oscillators is a known technique to improve the oscillator's phase noise performance. Generally, this is done by running two or more oscillators that are linked through a passive or active coupling mechanism. Therefore, the power consumption (at least) doubles, leading to no improvement regarding the standard figure-of-merit (FoM). This work discloses a new coupling mechanism for locked oscillators, that reuses the supply current and builds upon the fact that inverters implemented in modern CMOS processes are able to reach reasonable oscillating frequencies even without using the full nominal supply voltage range. Instead of instantiating the oscillators “side-by-side”, the propo scheme stacks oscillators between the supply terminal, thus reusing the drawn current at the same time as dividing the available supply voltage among the oscillators. Aiming for proper voltage division, we exploit a property of the ring oscillators, in which they are able to keep the same power consumption while the number of phases is increased/decreased. In the presented approach, the phase-noise performance improves without a penalty in power consumption, thus also improving the FoM. Simulation results show that by coupling two oscillators at f0and 2f0, the higher frequency oscillator locks and inherits the better phase noise performance of the lower frequency oscillator, while reusing the same current, demonstrating the effectiveness of the proposed topology.

Discrete-time ΣΔ generally rely on switched-capacitor implementations that require operational amplifiers to implement the integrators. For ultra-deep submicron processes, the limited intrinsic gain of the transistor hinders the design of operational amplifiers. This paper proposes a topology for ΣΔ modulators that employs a low-power quasi-passive integrator. The input voltage is converted into the chargedomain by a transconductor-based front-end. The integration process is implemented with MOS capacitors instead of linear capacitors, which allows the reduction of charge leakage. While this design targets relatively low resolutions, due to the nonlinear nature of the passive integration, the absence of operational amplifiers enables the topology to fit in a very small area. The topology is validated by simulations with the design of a 1storder ΣΔ modulator. The circuit is designed in a 0.13 μm technology, fits in 40 × 60 μm2, performs at 100 MSps with 51.34 dB of SNDR and consumes 0.08 mW.

We present a generic model for Multiple Phase Ring Oscillators (MPRO) with 2nphases, and derive equations for frequency, phase and phase error under the simplifying approach of injecting the error in a single element. Extensive Monte Carlo simulations, at transistor level, for the four and eight phase circuits, are in accordance with these assumptions. These results are validated by two prototype integrated circuits, implemented in a 130 nm CMOS technology: The first prototype, which is a standalone four phases Ring Oscillator (RO), validates the theoretical analysis concerning the non-linear model main conclusions and, the second prototype, which is an eight phase RO, incorporated as a block of an ISM receiver, validates the generic model for CRO concept.

Pulsars have been an object of research in several fields notably gravitational waves, the cosmos itself, deep-space navigation, plane localization methods, among others. Pulsar signals have periods ranging from miliseconds to seconds with extremely large period accuracy, comparable to that of atomic clocks. The pulsar signal itself also has a very large bandwidth These characteristics make conventional circuit simulation techniques unusable. This paper considers the characteristics of the pulsar signals and implements a prototype that generates a signal resembling the signals emitted by pulsars i.e., a pulsar generator. Such a simulator is very useful to assess pulsar receiver real time performance because pulsar signals are very difficult to capture on Earth due to its very low power, large bandwidth an also because of atmospheric effects which degrade the signal. The prototype allows to simulate different pulsar signals, in real time and is portable. Furthermore, the signal to noise ratio (SNR) can be adjusted from -14.9 to 19.7 dB and the signal bandwidth can me modified by using a set of different filters.

Pulsars emit broadband electromagnetic radiation, with an individual signature (period and shape), ranging from radio to X-ray and gamma-ray frequencies. For the purpose of navigation the pulsars of interest are fast rotating neutron stars that emit short stable periodic pulses, having periods between milliseconds and seconds. By detecting a set of known pulsars, it is possible to use them as beacons for navigation in celestial coordinates, being seen as the only truly navigation solution for deep-space navigation [1]. In this demo a proof of concept is presented for an innovative receiver architecture, overcoming, some of the issues presented in the paper entitled “Radio Pulsar Receiver Systems for Space Navigation” [2]. Furthermore, a fake pulsar generation board was developed and also an acquisition board, for both, simulate a pulsar signal and to process the data from the receiver and acquire the pulsar signal from noise.

This paper describes a course offered in the Master program in Electrical and Computer Engineering of Instituto Superior Técnico. The course is on analog integrated circuit design in mixed analog-digital context and is named Analog Integrated Systems (AIS). The novelty of this course is that it is organized on a top-down-top approach that allows a uniform distribution of workload throughout the 14 weeks semester. The pedagogical model chosen emphasize the practical design of an integrated circuit to comply with a given specification, while the students have all the freedom in choosing the approach to fulfil them. The course uses a professional CAD tool, “Cadence Design Framework II”, and the design flow procedure is in accordance with common practices used in the industry. The proposed model has been classroom tested in the last four years with positive student reviews on course quality assessment.

The vast majority of SAR ADCs on literature rely on very-linear capacitors to implement the DAC functionality. Still, if using the charge-sharing principle, a SAR ADC may employ MOS transistors used as capacitors (MOSCAPs) as DAC elements, benefiting from their higher capacitance density and broader availability. In this work, we exploit the body terminal of these MOSCAPs to adjust their capacitance and correct process mismatches. A background self-calibration scheme is presented and validated in a 12-bit 10 MSps SAR ADC. Post-layout simulations show that the algorithm is able to increase the effective-resolution of the ADC to 11.7 bits, in average. With a power consumption of 210 μW, the ADC achieves a figure of merit of 6.3 fJ/conversion-step. The presented ADC uses only 240 × 120 μm2of active area, including the calibration logic. Still, the deterministic calibration algorithm converges in less than 30k conversions. The achieved results make the proposed architecture very competitive for the range of moderate-resolution moderate-speed ADCs.

Non-destructive testing (NDT) based on eddy currents (EC) is commonly used to detect defects in conductive materials. Usually the system includes an emitter coil, and one receiver coil or one Magnetoresistive (MR) sensor. In this work we added an interface ASIC that pre-amplifies and filters the signal from an array of MR sensors. This demo will present a new version based on the work presented at the ECNDT 2014 conference with a paper entitled “A CMOS ASIC for Precise Reading of a Magnetoresistive Sensor Array for NDT”. Since this is an on-going work, improvements have been made, namely the reduction of the system thermal noise to 30 nV/√Hz, the development of a multigain amplifier and the application of the same concept and circuit to a multichannel parallel signal acquisition system. Detection of surface and buried defects will be demonstrated in different material mock-ups.

Interconnections are increasingly the dominant contributor to delay, area and energy consumption in CMOS digital circuits. Multiple-valued logic can decrease the average power required for level transitions and reduces the number of required interconnections, hence also reducing the impact of interconnections on overall energy consumption. In this paper, we propose a quaternary lookup table (LUT) structure, designed to replace or complement binary LUTs in field programmable gate arrays. The circuit is compatible with standard CMOS processes, with a single voltage supply and employing only simple voltagemode structures. A clock boosting technique is used to optimize the switches resistance and power consumption. The proposed implementation overcomes several limitations found in previous quaternary implementations published so far, such as the need for special features in the CMOS process or power-hungry current-mode cells. We present a full adder prototype based on the designed LUT, fabricated in a standard 130-nm CMOS technology, able to work at 100 MHz while consuming 122 μW. The experimental results demonstrate the correct quaternary operation and confirm the power efficiency of the proposed design.

This paper reports a successive approximation register (SAR) analog-to-digital converter (ADC) based on the charge-sharing principle, which is known to be very energy efficient, but susceptible to the comparator offset. The ADC uses a new background calibration technique to cancel out the comparator mismatch and improve ADC linearity. Operation under low voltages is obtained through the use of voltage-boosted switches in the track-and-hold and the digitalto-analog converter. The techniques are demonstrated on a low-voltage low-power SAR ADC that operates from a minimum supply voltage of 350 up to 600 mV, suitable for circuits supplied by power harvesters. The prototype fabricated in a 130-nm CMOS process employs only regular-VTH transistors. It is able to convert at 3 MSps when supplied by 600 mV and at 200 kSps when supplied by 350 mV. At 350 mV, the measured effective-number-of-bits is 6.4, leading to a figure-of-merit of 5.04 fJ/conversion-step.

Radio frequency energy harvesting circuits have to harvest energy from very weak sources demanding high sensitivity and high efficiency. In this paper, an efficient RF energy harvester for wireless sensor networks is presented. The circuit is based on a multi-stage rectifier that exploit threshold self-compensation together with transistor gate and bulk stimulus. The input is matched to 50Ω through a matching network that provides voltage boosting to the rectifiers input terminal. According to the desired performance, a 910MHz harvester with matched input comprising a 10-Stage rectifier has been designed in an 130-nm CMOS process. Considering a -20dB input power signal the circuit can supply a 1MΩ load with 1V/1μW output voltage and power with an PCE of 10%. The circuit exhibits a maximum PCE of 27% at -16dBm with 0.8V/6.4μW output voltage and power. The achieved results exceed the performance of previous work in terms of energy efficiency at input power lower than -15dBm.

CMOS RC oscillators have low area, can be built with a low cost technology, and have a wide tuning range, but they have higher phase-noise than LC oscillators. This can be overcome by synchronizing the oscillator by injection-locking with an low phase-noise external source. We present here an experimental study of injection-locking in an RC two-integrator oscillator. First and second harmonic injection in different locations of the oscillator are investigated. A test circuit was fabricated using a standard CMOS technology with 1.2 V supply. Measurement results show that a phase noise improvement of more than 30 dB, can be obtained with only -30 dBm injected signal between 100 kHz and 10 MHz frequency offset over a wide frequency range (600 MHz to 3 GHz).

RC oscillators have lower cost and higher tuning range than LC oscillators. However, their phase noise performance is poor and in the case of the relaxation oscillator it is also far from the theoretical optimum. In this paper we present a new circuit of a quadrature relaxation oscillator with faster switching and high amplitude output signal to improve the FoM. The sizing of a prototype in a 130nm CMOS technology was done using a genetic algorithm tool. Simulation results show that the quadrature oscillator operating at 2.4 GHz achieves a figure of merit of -165 dBc/Hz.

The comparator-based asynchronous binary-search (CABS) analog-to-digital converter (ADC) topology is a good solution to achieve high conversion rate at low power dissipation. In this paper we present an architecture of CABS ADC with a background calibration scheme, that allows the use of smaller devices, further reducing the power consumption. Unlike the foreground calibration, it does not require the ADC precalibration before it starts to operate, reducing the system-level complexity. The calibration is performed through the use of a digital-to-analog converter (DAC) serving as reference for the self-calibrated comparators. We also propose threshold reconfigurable comparators, reducing the number of the devices used. In this paper, we design a 7-bit 2-step ADC comprehending a 2-bit successive approximation register (SAR) ADC for the front-end and the proposed 5-bit CABS ADC for the back-end. Monte-Carlo simulations for the 2-step design show that, sampling at 250MSps, the ADC has 450μW of power consumption with a 6.92 effective number of bits resulting in a figure of merit of 14.86fJ/conversion step.

This work presents a new dynamically reconfigurable architecture that uses magnetic tunneling junctions to implement non-volatile reconfiguration memories. The magnetic-based storage elements further provide a very effective implementation of multi-context planes. The proposed architecture is organized as a 2-dimensional array of double precision floating-point run-time reconfigurable execution units. The configuration information defines the operation to be executed and the data flow intra and inter execution units. A prototype design of the coarse-grained reconfigurable array has been implemented targeting a 65nm CMOS technology. The obtained results confirm that the proposed architecture provides a significant computational density and that the magnetic memories provide a very area efficient multi-context based run-time reconfigurability.

Radio Frequency (RF) energy harvesting circuits have to harvest energy from very weak sources demanding high sensitivity and high efficiency. In this paper it is presented a study on rectifiers used in RF energy harvesting systems with MOSFET transistors operating in weak-inversion region, where both charge and discharge currents have the same order of magnitude. The study proves that the maximum output voltage of a MOSFET rectifier for very low input voltage is dependent in the first order to the relation between the signal amplitude and thermal voltage (VT). It is presented a method to calculate the maximum theoretical output voltage in two circuit topologies for input voltages of 10mV, 50mV and 100mV. The circuits are studied for 130nm, 90nm and 45nm CMOS technologies, proving the hypothesized theory that the maximum theoretical output voltage is not a function of the normal transistor parameters (i.e. Vt0, W/L) but instead, the relation between the input voltage amplitude and VT.

A wide range of applications, including wireless sensor networks (WSN) and biomedical, motivate the design of energy-efficient analog-to-digital converters (ADCs). We propose and discuss the design of an ultra-low power charge-sharing successive approximation ADC. The proposed ADC employs an internal step-down voltage regulator to reduce the energy spent on the digital-to-analog converter (DAC), and we demonstrate that this approach leads to a 5× reduction in the DAC power consumption. Moreover, a self-calibration technique is implemented in order to mitigate the impact of process variations on the ADC linearity. Simulation results show that the proposed 10-bit ADC, designed in a 90 nm technology, consumes 1.79 μW from a 1V supply, while sampling at 1 MSps and providing 9.34 effective bits (mean values based on Monte-Carlo simulation). The achieved figure-of-merit (FOM) of 2.87 fJ/conversion step (mean value) places this ADC among the state-of-the-art designs in low-speed moderate-resolution ADCs.

Modern RF communication technologies often shift the baseband processing to the digital domain, thus requiring an analog-to-digital converter (ADC) as interfacing element. For most applications, those ADCs must provide very-high conversion rate at low cost (effective in terms of area and power). We propose an improved binary-search ADC topology, which relies on a pipeline of threshold-reconfigurable comparators and a time-interleaved track-and-hold arrangement. We also propose a topology of threshold-reconfigurable comparator and a corresponding effective design methodology based on optimization through genetic algorithms. In this paper, we design a proof-of-concept 5-bit ADC which does not require calibration as most similar designs. Monte Carlo simulations for the proposed design show that, sampling at 1.5 GSps, the ADC consumes 5 mW providing 4.6 effective bits and a figure of merit of 138 fJ/conversion step (mean values).

This paper describes the implementation of an IR-UWB transmitter using an oscillator, and where the pulse duration is controlled digitally by the oscillator frequency. In this new topology, the consumption is reduced to the leakage current when it is not producing a pulse, ensuring high power efficiency even for low data rates. The proposed circuit is inductorless and implemented in a standard UMC 130nm CMOS technology to be die area efficient and low cost. The design and simulation results are presented, including pads and off-chip elements as bonding wires and antenna models. The transmitter die area with pads is 0.0783 mm2, and the energy consumption per pulse is 25.5 pJ from a 1.2 V supply.

This paper describes an integrated digital-to-analog converter (DAC) for a intra-cortical microelectrode stimulator. The circuit has a special feature that consists on charging and discharging the same current to prevent electric charge accumulation that might harm the brain. The DAC has 5 bits of resolution supplying a maximum current of 100 µA to one electrode of the cortical stimulator. The circuit is sized to operate at a maximum sampling frequency of 1 MHz, has an active area of 0.077 mm2, and the biasing part consumes only 19.2 µA, from a 3.3 V supply voltage. The circuit has low area to reduce its impact inside the brain and is low power to allow using wireless energy harvesting circuits preventing the use of batteries or wires, to reduce the risk of infections. A circuit prototype was implemented in AMS 0.35um CMOS technology, and tested.

Analog designers are challenged by increasingly complex device models and lowered signal swing as the CMOS processes scale. At the same time, new trends and emerging technologies pose tighter design constraints. However, the cheap computational resources nowadays enable the use of the mature electrical simulators and device models in simulation-in-a-loop optimization techniques. In this work, we present a flexible circuit optimization tool for analog designs which relies on evolutionary algorithms. Moreover, we employ logistic functions to determine the fittest individuals. The benchmarking test shows that the program is able to dimension an operational transconductance amplifier (OTA) based on the topology netlist in less than 15 minutes, without resorting to any knowledge base, initial guess or simplified models. The achieved performance suggests that the tool may be integrated in an existing design flow with huge benefits.

We present a new RC relaxation oscillator with pulse self biasing, to reduce power consumption, and with harmonic filtering and resistor feedback, to reduce phase-noise. A circuit prototype in the hundreds of MHz range, designed in a 130 nm CMOS technology has a very low phase-noise, -132.6 dBc/Hz @ 10 MHz offset, and the power consumption is only 1 mW, which leads to a figure of merit (FOM) of -159.1 dBc/Hz.

This paper describes the implementation of an RF receiver frontend for the 2.4 GHz ISM band; it comprises an LNA, an IQ oscillator/mixer, and a low-pass filter. The proposed circuit is low cost and power efficient. To be low cost the circuit is inductorless and implemented in a standard nanoscale digital CMOS technology, with a state-of-the-art figure for area. To be power efficient all the circuits were chosen based on their power efficiency. A contribution in this paper is a new, more efficient, IQ oscillator/mixer block, where the current is reduced by 25% and reused for the two functions. A prototype of a low-IF receiver frontend is designed in UMC 130nm CMOS technology and simulated with a post-layout including pads netlist, and off chip elements as bonding wires and load models. The frontend active area is 0.051 mm2(die area with pads is 0.395 mm2), and the power consumption is 16.3 mW from a 1.2 V supply for a frontend gain of 27 dB.

In this work we present a prototype circuit to harvest energy from radio frequency (RF) electromagnetic waves based on an integrated transformer together with a half-wave multi-stage rectifier. This circuit is designed to be impedance matched to a standard 50 Ω antenna and to operate at 2.4 GHz with input power as low as -15 dBm. The circuit presented here shows that it is possible to harvest low power input signals and therefore it can be used to supply alone a circuit, or to work as a backup battery charger. The circuit was designed and simulated in a standard 130 nm CMOS process.

Modern Ultra-Wide Band (UWB) regulations have recently been adopted worldwide allowing for unlicensed operation within 3.1 and 10.6 GHz, using an appropriate wideband signal format with a low Effective Isotropic Radiated Power (EIRP) level. UWB characteristics are suitable to transmit data using pulses instead of continuous-waves such as in narrowband radio links. It has the potential to be the right technology for high data-rate, low-power and short-to-medium range communication systems. We will focus on Impulse Radio-UWB (IR-UWB) systems and show their suitability for many different applications, including sensor networks, ad-hoc networks, cognitive radio, home networking, etc. We will also discuss the difficulties and challenges of designing IR-UWB systems. We present a tutorial overview of UWB regulations and usable signals. We present the existing standards and recommendations, and we review recently published results, highlighting trends in UWB transceiver power consumption and the impact of CMOS scaling on performance.

This paper presents the implementation of a coarse-grained magnetic RAM based reconfigurable array. The reconfigurable array architecture is organized as a one-dimensional array of programmable ALU, with the configuration bits stored in magnetic random-access memories. The use of MRAM technology to implement run-time reconfigurable hardware devices is a very promising technological solution because MRAM can provide non-volatility with cell areas and access speeds comparable to those of SRAM, and with lower process complexity than flash memory. This type of coarse-grained array, where each reconfigurable element computes on 4-bit or larger input words, is more suitable to execute data-oriented algorithms and is more able to exploit larger amounts of operation-level parallelism than common fine-grained architectures. By substantially reducing the overhead for configurability, this coarse-grain architecture is also more apt to efficiently exploit run-time reconfiguration and therefore to take advantage of multi-context MRAM-based configuration memories.

We present a combined LNA-mixer circuit with low area and low power, for the 2.4 GHz ISM band. The circuit has two versions: one has an output RC low-pass filter suitable for low IF frequencies; the other has an output LC band-pass filter suitable for medium IF frequencies. Circuits, with IF of 50 MHz and 400 MHz, were designed using UMC 0.13 mum CMOS technology and 1.2 V supply, and dissipate approximately 7.6 mW.

In this paper we investigate the performance of the multi-band low noise amplifier (LNA) based on the concept of using multiple cascode transistors for band selection; thus, avoiding switches in the signal path. We also show that this circuit can perform mixing of two signal bands with two different local oscillator frequencies, which provides great flexibility in the design of dual-band RF front-ends. The operation of both as LNA and as combined LNA/mixer is demonstrated by simulation.

This paper considers two oscillators (van der Pol or Robinson type) synchronized using capacitive coupling. Equations are derived for the oscillation frequency and amplitudes. They show that the frequency of synchronous oscillation is different from the frequencies of individual oscillators. The amplitudes of oscillation are also different: one oscillator becomes a master and the second oscillator becomes a slave. A method of quasilinear approximation is used to evaluate the stability of synchronous oscillation. Simulation results for a 5 GHz oscillator confirm the theoretical analysis.

In the last years we have assisted to a great development of wireless receivers working in narrow frequency bands. Nowadays, this development goes towards more flexible wireless receivers which accommodate different wireless applications - wide-band and multi-band receivers. In this paper we study techniques suitable for the design of dual-band CMOS low noise amplifiers (LNA), based on cascode switching and inductor magnetic coupling. Two LNA topologies were evaluated and implemented in a 0.35μm CMOS process. A proof of concept, a prototype of a proposed dual-band CMOS LNA was designed to work simultaneously at 0.9 GHz and 1.8 GHz. It uses a voltage supply of 2.4 V consuming 4.8 mA.

Contrary to what happens with LC oscillators, the increase of coupling in cross-coupled relaxation RC-oscillators leads to a lower quadrature error and lower phase-noise. We present a 2.4 GHz CMOS quadrature relaxation oscillator, and show the measurements confirming this property. Increasing the coupling block gain, the oscillator phase-noise is reduced from -97 dBc/Hz to -104 dBc/Hz @ 1 MHz. The quadrature error is reduced from 4.3deg to 0.8deg. These results show that RC quadrature oscillators may be a practical alternative for RF transceiver applications.

It is shown that synchronization is similar to amplitude stabilization: both mechanisms involve creation of harmonics and frequency reduction. Synchronization of LC-oscillators can be achieved using similar synchronizing circuits in each oscillator connected in parallel with the tank. The output of the first synchronization circuit is routed to the second oscillator and vice versa. This scheme provides coupling using first, third and other odd harmonics. In addition, introducing coupling between common mode outputs of the synchronizing circuits provides second and other even harmonic coupling. This type of coupling may be also used between common mode outputs of amplitude stabilization circuits. The benefits of using simultaneous first and second harmonic coupling were verified designing a low-power, low phase noise 5 GHz LC oscillator with quadrature outputs. The oscillator phase noise is lower than -121.2 dBc/Hz at 1-MHz offset over the tuning range with a power consumption of 1.8 mW achieving a FOM lower than -192.2 dBc/Hz

In this paper, an IQ oscillator/mixer circuit is presented in which the mixers are an integral part of the oscillator. The oscillator alone has accurate quadrature outputs, even in the presence of component mismatch. This precise quadrature is preserved when mixers are incorporated in the oscillator. An oscillator/mixer core for a carrier frequency of 5 GHz, suitable for a low-IF front-end, was designed and tested. The power consumption is 30 mW from a 2.5 V supply, and a phase error of 1deg was measured

A new coupling mechanism is used to synchronize two Van der Pol oscillators. This coupling uses the second harmonic appearing in common mode current of each oscillator. The common mode current is measured by a current mirror, and is amplified by a current amplifier. The amplifier introduces negative feedback, so that the current in the current mirror measuring diode of the first oscillator is nearly equal to the common mode current of the second oscillator, hence the coupling is established. It is shown that the system of two oscillators is described by two differential equations where the coefficients in one equation have the perturbations defined by the second oscillator, and vice versa. The coupling amplifier gain is defined. The developed concepts are demonstrated on a 5 GHz CMOS LC oscillator with quadrature outputs. The oscillator phase noise is lower than -116 dBc/Hz at 1-MHz offset

For full-parallel, 2-step parallel, and pipelined parallel ADCs (Analogue to Digital Converters) we establish the relationship between the comparator's input offset voltage and the yield. The yield is defined by three different criteria: absence of missing codes, and either integral or differential nonlinearity below a specific value. The results obtained are confirmed by computer statistical simulation.>