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Kyohei Yamaguchi

dblp:44/3553 · DBLP profile ↗
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4ranked-venue papers
1as first author
0since 2021 · last 2013
0000-0001-5284-2128ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-authorArtificial intelligence and machine learning · 2Human-computer interaction and ubiquitous computing · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 56% Memory systems · 44%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › memory access optimization
memory-level parallelism
0.212013
MLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLP · MICRO 2013
Processor architecture and microarchitecture
out-of-order execution
0.212013
MLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLP · MICRO 2013
Processor architecture and microarchitecture
instruction-level parallelism
0.012013
MLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLP · MICRO 2013

Methods — techniques the papers use, named apart from their topics

MLP-aware resizing · 0.2
YearPublicationVenuePosition
2013 MLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLP
abstract
It is difficult to improve the single-thread performance of a processor in memory-intensive programs because processors have hit the memory wall, i.e., the large speed discrepancy between the processors and the main memory. Exploiting memory-level parallelism (MLP) is an effective way to overcome this problem. One scheme for exploiting MLP is aggressive out-of-order execution. To achieve this, large instruction window resources (i.e., the reorder buffer, the issue queue, and the load/store queue) are required; however, simply enlarging these resources degrades the clock cycle time. While pipelining these resources can solve this problem, this leads to instruction issue delays, which prevents instruction-level parallelism (ILP) from being exploited effectively. As a result, the performance of compute-intensive programs is degraded dramatically.
Yuya Kora, Kyohei Yamaguchi, Hideki Ando
MICRO2
2012 Improvement of assistive wheelchair caster unit for step climbing
abstract
The objective of this study is to develop the mechanism which assists the wheelchair user to climb a step. The wheelchair caster unit with an assistive mechanism is developed. This unit is easily replaced with the conventional wheelchair caster. The proposed caster unit has two functions to assist the step climbing. One is the assistive plates to enlarge the caster radius imaginarily. The other is a lock-function to yaw axis caster rotation, which realize easy climbing with oblique approach. Our first prototype shows good performance for above mentioned two functions, and can assists step climbing. However, the first prototype is heavy, because of the electromagnetic tooth clutch is used for the lock-function. Therefore this paper improve the lock-function of first prototype, and report the outline of the new prototype. The new lock-function was composed by the solenoid, the rack and pinion gear. By using the solenoid, the unit realizes weight and cost saving and low power consumption, and it is more practical design than first prototype.
Sho Yokota, Hiroyuki Tanimoto, Junki Heguri, Kyohei Yamaguchi, Daisuke Chugo, Hiroshi Hashimoto
RO-MAN4
2011 Evaluation of issue queue delay: Banking tag RAM and identifying correct critical path
abstract
The tradeoff between complexity and attained instructions per cycle is often an important issue in microarchitectural designs. In this design phase, quick quantification of the complexity (i.e., delay) of relevant structures is required. The issue queue is one of such complex structures for which it is difficult to estimate delay. In this paper, we evaluate the issue queue delay to aid microarchitectural design. Our study includes two features: a circuit design and evaluation. First, we introduce banking the tag RAM, which is one of the components comprising the issue queue, to reduce the delay. Unlike normal RAM, banking the tag RAM is not straightforward, because of its uniqueness in the organization of the issue queue. Second, we explore and identify a correct critical path in the issue queue. A previous study summed the critical path of each component in the issue queue to obtain the delay of the issue queue, but this does not provide the correct delay of the issue queue, because the critical paths of each component are not connected logically. In the evaluation assuming 32nm LSI technology, we obtained the delays of an issue queue with eight to 128 entries. The process of banking the tag RAM and identifying the correct critical path reduces the delay by up to 20%, compared with not banking the tag RAM and simply summing the critical path delay of each component.
Kyohei Yamaguchi, Yuya Kora, Hideki Ando
ICCD1
2007 Measuring and modeling active maximum fingertip forces of a human index finger
abstract
The present paper develops a model of "active" fingertip forces of a human index finger that allows the maximum fingertip force to be calculated for any specified position of the finger. The proposed model extends a passive fingertip force model by considering the mobility of the fingertip in terms of its deformation. The model selects the smaller force of the following two forces: the maximum force calculated using the musculoskeletal model and the maximum force calculated using the maximum deformation depth of the fingertip that lies within the ranges of motion of all the joints. A further extension of the previous passive fingertip force model is that a nonlinear relationship between muscle length and exerted force is considered. Maximum active fingertip forces were measured for three subjects and compared with the forces calculated using the proposed model and the previous model. The results of our model were in good agreement with the measured forces in contrast with the large values obtained using the passive fingertip force model.
Natsuki Miyata, Kyohei Yamaguchi, Yusuke Maeda
IROS2