This paper presents the design of a scalable face recognition system to address real-world challenges including illumination-variation, occlusions and motion blur. This proposed method integrates multiple state-of-the-art models into a unified pipeline: YOLOv5-Face is used for preparation of the dataset, SCRFD for face detection with high accuracy and face alignment, ArcFace for discriminative feature embedding generation and BYTETracker for continuous multi-face tracking. Experimentations conducted on a locally generated dataset demonstrate strong performance by achieving the training accuracy of 90.13%, validation accuracy of 89.02%, and a ROC AUC score of 0. 9 5 9 2. The system is able to sustain real-time performance with 25-30 FPS and low latency of 33-40 ms per frame. These results make this system suitable for largescale surveillance applications. The results also highlight the effectiveness of multi-model integration in improving the accuracy and adaptability when compared to traditional approaches. This paper contributes a practical solution for deployment in the domains such as campus surveillance, access control and crowd monitoring. It also provides foundation for future work which include liveness detection, super-resolution for low resolution recognition and lightweight edge-compatible model implementation.

One of the key technologies of next-generation 6G networks is millimeter-wave communications that will deploy a large number of antennas at the base station enabling narrow beams toward user locations to mitigate the path loss. Conventional methods have resulted in high training overhead in finding the best beam pair to obtain beam alignment between the base station and a user. This paper proposes a data-driven neural network approach to intelligently perform the beam selection between the transmitter-receiver pair. We propose a convolution neural network (CNN) based beam selection method trained from simulator-generated beam dataset. We use skip connections and hyperparameter optimization to balance the trade-off in accuracy and computational complexity. We validate the efficacy of our proposed method by comparing it with other conventional and machine learning-based approaches. Evaluation results show higher accuracy (> 70%) while reducing the computational complexity upto 15%.

We present a novel technique for Sequential Equivalence Checking (SEC) between non-cycle-accurate designs. The problem is routinely encountered in verifying the correctness of a system-level model versus an RTL design which has been derived from the former either manually or through high-level synthesis. The existing state-of-the-art in formal verification/SEC does not provide an efficient mechanism to perform such an equivalence check. Our technique reduces the SEC problem to a cycle-accurate equivalence-checking problem by constructing a pair of normalized cycle-accurate designs from the original designs, on which standard equivalence-checking techniques can then be deployed. We report the results of deploying our techniques on several industrial examples.

It has long been the practice to create models in C or C++ for architectural studies, software prototyping and RTL verification in the design of Systems-on-Chip (SoC). It is often the case that by the end of a design project, multiple C models exist for different uses. Clearly, this leads to wasted effort on the part of model developers, and creates risk of functional divergence across models. In this paper we present some guidelines for system-level modeling and RTL design to allow for efficiently leveraging the system-level model for RTL verification via simulation based techniques, as well as via sequential equivalence checking. The paper presents the challenges of keeping system-level models and RTL synchronized from a functional perspective and presents some techniques for overcoming these challenges.

A rigorous system-level model (SLM) for a hardware design project is extremely important, often critical. Such a functional model not only defines the architect's ideas but also builds a precise foundation for both hardware designers and verification engineers. The key uses of SLMs are: architecture validation; performance modeling and architectural trade-off; platforms for software development and verification; and functional reference model. In this tutorial, we discuss how to formally verify sequential equivalence between SLMs and RTL, for both timed and untimed models. First, we provide a formal definition of the sequential equivalence. Then we discuss various formal verification technology that enables such practice in real designs.

Abstract: We introduce the notions of required precision and information content of datapath signals and use them to de ne functionally safe transformations on data ow graphs. These transformations reduce widths of datapath operators and enhance their mergeability. Using e cient algorithms to compute required precision and information content of signals, we de ne a new algorithm for partitioning a data ow graph consisting of datapath operators into mergeable clusters. Experimental results indicate that use of our clustering algorithm for operator merging based synthesis of datapath intensive designs, can lead to signi cant improvement in the delay and area of the implementation. 1.

Finding the set of steady states of a machine has applications in formal verification, sequential synthesis and ATPG. Existing techniques assume the presence of a designated set of initial states which is impractical in a real design environment. The set of steady state of a design is defined by the terminally strongly connected components (tSCCs) of the underlying state transition graph (STG). We show that multiple tSCCs and non-terminal SCCs need to be handled in a real design environment especially for verification. We present a fully implicit algorithm to find the steady states of a machine without any knowledge of initial states. We demonstrate the utility of our algorithm by applying it to FSM equivalence checking.

The use of multi-phase clocking scheme, aggressive pipelining and #sparse" encodings in high performance designs results in a tremendous increase in the state space. In this paper, we show that automatically transforming such designs to ones that have more #dense" encodings can result in signi#cant bene#ts in using implicit BDD-based techniques for their veri#cation. We formulate a relaxed retiming framework which is more powerful than traditional retiming in reducing the number of latches and show that it can be applied to the product machine model for checking sequential hardware equivalence #SHE# without altering the correctness of the SHE check. We combine retiming with phase abstraction #4# #a technique to transform multi-phase FSMs to single-phase FSMs for equivalence checking#. The two transformations enable the SHE check to be performed on high performance controllers with large state space #more than 100 latches# from an industrial setting. 1 Introduction Due to aggressive t...

Equivalence checking of finite state machines (FSMs) traditionally assumes single phase machines where a single clock (implicit or explicit) synchronizes the state of the FSM. We extend the equivalence checking paradignm to FSMs with multi-phase clocks. Such designs are becoming increasingly popular in high performance microprocessors since they result in lower synchronization overhead. In addition, aggressive pipelining and the use of “sparse” encodings results in designs where the ratio of steady states to the total state space is very low. In this paper, we show that automatically transforming such designs to ones that have more “dense” encodings can result in significant benefits in using implicit BDD-based techniques for their verification. We explore two such techniques: phase abstraction and retiming and demonstrate their utility in the context of FSM equivalence checking. The main contributions of our work are: —We show that a multi-phase FSM can be transformed to a functionally equivalent one phase FSM and this phase abstraction leads to significant improvement in the size of FSMs that can be checked for equivalence. —We show that min-latch retiming preserves equivalence and can be performed efficiently in multi-phase designs, even when latch borrowing and discarding is allowed at the primary inputs and outputs. —We demonstrate the utility of our approach on several controller FSMs from the industry.

Embedded systems consist of interacting components that are required to deliver a specific functionality under constraints on execution rates and relative time separation of the components. In this article, we model an embedded system using concurrent processes interacting through synchronization. We assume that there are rate constraints on the execution rates of processes imposed by the designer or the environment of the system, where the execution rate of a process is the number of its executions per unit time. We address the problem of computing bounds on the execution rates of processes constituting an embedded system, and propose an interactive rate analysis framework. As part of the rate analysis framework we present an efficient algorithms for checking the consistency of the rate constraints. Bounds on the execution rate of each process are computed using an efficient algorithm based on the relationship between the execution rate of a process and the maximum mean delay cycles in the process graph. Finally, if the computed rates violate some of the rate constraints, some of the processes in the system are redesigned using information from the rate analysis step. This rate analysis framework is implemented in a tool called RATAN. We illustrate by an example how RATAN can be used in an embedded system design.

Formally verifying properties of signals in a circuit hasseveral applications in an equivalence checking based formalverification flow.In a hierarchical design, functionalityis divided across blocks.This necessitates the useof constraints on input signals of a block to avoid falsenegatives.Validating such input constraints requires assertionchecking at the outputs of modules generatingthe constrained signals.In this paper, we present anefficient assertion checker for combinational propertieswhich avoids the BDD explosion problem by finding anoptimal intermediate correlation free frontier.It hasbeen successfully used in an industrial setting to uncovera number of bugs.

We present a new iterative algorithm for timing-driven placement applicable to regular architectures such as field-programmable gate arrays (FPGAs). Our algorithm has two phases in each iteration: a compression phase and a relaxation phase. We employ a novel compression strategy based on the longest path tree of a cone for improving the timing performance of a given placement. Compression might cause a feasible placement to become infeasible. The concept of a slack neighborhood graph is introduced, and is used in the relaxation phase to transform an infeasible placement into a feasible one using a mincost maxflow formulation. The slack neighborhood graph approach used in the relaxation phase guarantees a bounded increase in delay during the relaxation phase. Our analytical results regarding the bounds on delay increase during relaxation are validated by the rapid convergence of our algorithm on benchmark circuits, We obtain placements that have 13% less critical path delay (on the average) than those generated by the Xilinx automatic place and route tool (apr) on technology-mapped MCNC benchmark circuits. The running time of our algorithm is significantly less than that of apr. Slack neighborhood graphs are of independent interest because they can also be used for timing-driven reconfiguration for yield enhancement and for handling incremental design changes efficiently.

A function $f:\Re \to \Re $ is k-modal if its kth derivative has a unique zero. We study the problem of finding the smallest possible interval containing the unique zero of the kth derivative of such a function, assuming that the function is evaluated only at integer points. We present optimal algorithms for the case when k is even and for $k = 3$ and near-optimal algorithms when $k \geqslant 3$ and odd. A novel generalization of Kraft’s inequality is used to prove lower bounds on the number of function evaluations required. We show how our algorithms lead to an efficient divide-and-conquer algorithm to determine all turning points or zeros of a k-modal function. Unbounded k-modal search is introduced and some problems in extending previous approaches for unbounded searching to the k-modal case are discussed.

In this paper we examine three different problems related to FPGA placement: timing driven placement of a technology mapped circuit, timing driven reconfiguration for yield enhancement and fault tolerance in FPGAs and timing driven design re-engineering for FPGAs. We show that timing driven relocation which transforms an infeasible placement into a feasible one is a key problem the solution of which will lead to good algorithms for all three of these optimization problems. We introduce the concept of a slack neighborhood graph (SNG) as a general tool for timing driven relocation of modules in an infeasible placement with a bounded increase in critical path delay. The slack neighborhood graph approach provides a unified approach to the solution of three timing driven optimization problems of interest in this paper.

In a typical design flow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design specification either as a result of design debugging or as a result of changes in engineering requirements. These modifications are usually local and are referred to as engineering changes. In this paper we study the problem of timing driven placement re-engineering: the problem of altering the placement of a circuit to incorporate engineering changes without degrading the timing performance of the circuit. We focus on the re-engineering problem for regular architectures such as FPGAs and gate arrays. Our algorithms exploit the locality of the re-engineering design changes and use the current placement to generate the new placement for the altered circuit. Our experiments on the Xilinx 3000 FPGA architecture demonstrate the effectiveness of our algorithm in handling engineering changes efficiently.