Noise-shaping successive approximation register (NS-SAR) ADCs combine high resolution with energy efficiency, but their performance degrades at bandwidths in the tens of MHz due to limited oversampling ratios (OSR) and adoption of low-order passive filters. This work introduces a$3{^{\text {rd}}}$-order NS-SAR ADC that leverages a multi-input amplifier and a multi-input comparator, enabling independent optimization and flexible filter coefficient sizing. In addition, a ratio-based floating inverter amplifier ensures remarkable gain stability across process, voltage, and temperature (PVT) variations. Implemented in a 28-nm CMOS process, the prototype achieves 12.3-ENOB over a 20-MHz bandwidth while consuming 1.56 mW, resulting in a Schreier figure-of-merit (FoMS) of 177-dB with robust and consistent performance across PVT corners.

This paper analyses for the first time from a quantitative standpoint the effectiveness of redundancy in successive approximation register (SAR) analog-to-digital converters (ADCs) that employ the conventional and monotonic switching algorithms. It is shown that the redundancy tolerance window is one-sided in the case of conventional switching algorithm, thus only underestimations of the input signal can be corrected. Conversely, the monotonic switching algorithm shows a symmetric tolerance window that allows the correction of both underestimations and overestimations of the input signal. Thermal noise due to switches and comparator, and supply bouncing cause both these errors and they can be effectively corrected only with a symmetric redundant window. Behavioral simulations confirm that the monotonic switching algorithm applied to redundant SAR ADCs achieves better performance than the conventional one in terms of signal-to-noise-and-distortion ratio (SNDR).

This paper presents a novel technique to reduce the locking time in Digital Phase-Locked Loop (DPLL) based on Bang-Bang Phase Detector (BB-PD). The implemented 65-nm CMOS fractional-N frequency synthesizer generates an output signal between 3.7 and 4.1 GHz from a 52 MHz reference clock and improves the trade-off between phase noise, due to the loop quantization, and locking time, exploiting a digital locking loop that avoids look-up table (LUT) and finite state machine-based (FSM) locking schemes. Measurements show that the output signal spot noise at 20 MHz from the carrier is −150.7 dBc/Hz while the best locking time, for a coarse step of 364 MHz, is 115$\mu \text{s}$, overcoming the locking time limitations and avoiding cycle slips that usually affect the 1-bit phase detector PLL.

This work introduces an accurate linearized model and phase noise spectral analysis of digital bang-bang PLLs, that includes both the reference and the digitally-controlled oscillator (DCO) noise contributions. A time-domain analysis of bang-bang PLLs is leveraged to derive closed-form expressions for the integrated jitter, leading to a precise estimation of the binary phase detector (BPD) equivalent gain. The theoretical predictions differ by less than 1% from the simulation results obtained using a behavioral model, in all typical cases: dominant reference noise, dominant DCO noise, and comparable contributions. An accurate discrete-time model that takes into account the time-variant effect arising from the multirate nature of a digital phase-locked loop (DPLL) is used, along with the provided estimation of the jitter, to predict the output and input-referred phase noise spectra. An excellent match with the simulated spectra is achieved for all the different operating conditions.

This paper analyses the noise performances of coupled phase-locked loops, providing closed-form expressions for the transfer functions of the various noise sources, and presents a novel coupling topology, whose goal is the reduction of both in-band and out-of-band phase-noise. The proposed circuit consists of two, or more, standard loops coupled via an additional phase detector. It will be demonstrated that in this architecture the impact of the main PLL noise sources, the oscillator and the reference buffer, is efficiently traded with the power dissipation without resorting to lossy and area-consuming passive coupling networks. The work then shows how to derive the set of design parameters that grant the desired performance for a given case study. The entire procedure is verified by simulations.

The direct frequency modulation of a phase locked loop suffers from limited modulation bandwidth. To overcome this limitation, the modulation signal can be pre-emphasized by means of a high-pass filter. Unfortunately, the incorrect equalization of the PLL transfer function causes modulation error. This paper introduces a new method to adaptively match the transfer functions of the PLL and the pre-emphasis filter over environmental and process variations. The technique is verified using a time-domain model of a digital PLL designed for the generation of chirp signals for FMCW radar sensors. The new adaptive digital pre-emphasis technique enables the generation of highly-linear fast chirps with significant reduction of the idle time.

This paper discusses the impact of CMOS scaling in the design and performance of switched-capacitor power amplifiers operating in the sub-GHz bands for Internet-of-Things applications. While the peak drain efficiency is found to improve by about 10% when the amplifier is scaled down from a 65-nm standard CMOS to a 28-nm fully-depleted SOI CMOS process, the average efficiency instead slightly degrades. Moreover, it is theoretically demonstrated that the power density (peak-power over area-occupation) is a function of the supply voltage and the dielectric constant of the switched capacitor insulator and it is about 13% higher in the 65-nm CMOS node.

In today's fractional-N phase-locked loops, digital-to-time converters are commonly used to cancel the quantization noise of the divider modulus, and a least-mean squares loop is used to adapt the gain of the cancellation path. Unfortunately, a trade-off exists between the time range needed to the digital-to-time converter and the speed of convergence of the calibration. In this paper, a novel scheme significantly relaxing this trade-off and allowing for a low-power implementation of both the digital-to-time converter and the calibration loop, is introduced. The effectiveness of the proposed concept is verified via behavioral simulations in the presence of circuits non-idealities, showing a reduction of at a least a factor of 5× in the settling time of the calibrated coefficient.

The need for low-noise, highly-linear, programmable chirp generators makes digital phase-locked loops (DPLLs) an attractive solution for radar sensors. This paper presents a general analysis and comparison of the two main techniques enabling wideband frequency modulation (FM) in PLLs, namely the two-point injection and the pre-emphasis. It is shown that while the two topologies are equivalent in term of mismatch error suppression, the required input range for the time-to-digital converter (TDC) is substantially lower in the two-point injection scheme, thus relaxing the TDC power consumption and linearity.

The adoption of the digital/time converter (DTC) circuit has improved the performance of ΔΣ fractional-N phase-locked loops (PLLs). Accurate cancellation of ΔΣ quantization error via the DTC requires an automatic calibration made by an LMS loop. A high-order ΔΣ speeds up calibration convergence and improves PLL spectral purity, though at the price of larger quantization error and wider DTC range. To overcome this problem, we propose an innovative parallel segmentation scheme which reduces the range of quantization error without compromising spectral purity and convergence speed. The effectiveness of the proposed segmentation scheme is demonstrated via behavioral-level simulations of a digital PLL and compared to the conventional cascaded segmentation scheme.

This paper presents a digital background linearization technique for high-speed Nyquist-rate digital-to-analog Converters (DACs), based on the use of a least-mean-square (LMS) multipath adaptive filter that continuously measures and cancels non-linearity arising from static errors. In contrast to previously-published correlation-based techniques, the proposed method is not limited to the cancellation of component mismatches, but it performs the correction of the overall static characteristic regardless of the source of non-linearities. It requires only an additional low-speed accurate DAC and moderate digital hardware complexity, avoiding the need for a multibit analog-to-digital converter. The effectiveness of the proposed technique applied to a current-steering DAC suggests that it could be useful to overcome the typical high-speed DAC trade-off, allowing the elimination of static non-linearity errors without sacrificing dynamic performances.

Digital phase-locked loops based on bang-bang phase detectors are attractive candidates for frequency synthesizers and clock multipliers because of their simplicity and low power consumption. However, being nonlinear systems, they are proved difficult to analyze and prone to the generation of limit cycles. Under the presence of phase noise originating from the controlled oscillator with 1/f2and 1/f3spectral shapes, simple expressions of the output jitter as a function of the loop parameters are developed which allow us to avoid limit cycles and to optimize the design to minimize output jitter.

This paper provides an original and very efficient computational method to evaluate phase-noise effects in injection-locked frequency dividers. The technique relies on a realistic phase-domain macromodel of the locked oscillator whose parameters are extracted by means of an RF circuit simulator.

This paper introduces a technique for suppressing the effect of deterministic jitter in phase-locked loops based on multiplying delay-locked loops. A digital loop operating in background of normal operation detects the static phase offset between the two reference-signal paths by means of a single-bit time-to-digital converter and compensates for it by means of a digital-to-time converter.

This paper describes a simulation method to compute oscillator phase noise which combines transient and periodic-transfer-function analyses, available in most of the commercial circuit simulators. The proposed calculation technique is simple to implement and provides the designer a deep insight into phase noise generation mechanisms for both stationary and cyclostationary sources, thus resulting a powerful tool to perform an optimum design in RF applications.

The mismatch-induced fractional spurs have so far limited the adoption of phase-interpolation-based fractional-N PLLs. Only recently a background cancellation technique, embedded in a digital fractional-N PLL, has faced this issue. In this paper, we will show that this technique is equivalent to a multi-path adaptive circuit that cancels the effects of the phase interpolator non-linearity. This analysis allows highlighting the speed/accuracy trade-off inherent in these algorithms. Simulation results verify the validity of the proposed approach.

This work proposes two novel simulation techniques that allow for fast and accurate predictions of phase noise in oscillators even adopting inexpensive software, such as PSpice. The traditional harmonic tone insertion is initially discussed, by applying it to a LC-tuned oscillator taken as benchmark. Then a first, much faster technique based on sensitivity analysis is proposed, which is suitable for the estimation of phase noise due to low-frequency sources, e.g. 1/f noise. Finally, the high-frequency noise sources contributions to SSCR are analyzed through another alternative method based on the frequency demodulation of the carrier. Both of these methods allow the designer to promptly identify the noise sources mainly responsible for the carrier instability and to accomplish the optimization for low phase noise of the synthesizer.

VCO for wireless receivers must fulfil tight requirements of phase noise and their complete integration in silicon VLSI technologies is still an open issue due to the low quality factor of the inductors. In this paper we address some of the constraints met in the design of low noise oscillator stages: the tank topology and its quality factor, the dynamics of the transconductor stage and its loading effects, the limitation resulting from the AM-to-PM conversion.