On-Chip Variation (OCV)-aware and Path-Based Analysis (PBA) accurate timing optimization achieved by gate sizing (including Vth-assignment) remains a pivotal step in modern signoff. However, in advanced nodes (e.g., 3nm), commercial tools often yield suboptimal results due to the intricate design demands and the vast choices of library cells that require substantial runtime and computational resources for exploration. To address these challenges, we introduce LEGO-Size, a generative framework that harnesses the power of Large Language Models (LLMs) and GPU-accelerated differentiable techniques for efficient gate sizing. LEGO-Size introduces three key innovations. First, it considers timing paths as sequences of tokenized library cells, casting gate sizing prediction as a language modeling task and solving it with self-supervised learning and supervised fine-tuning. Second, it employs a Graph Transformer (GT) with a linear-complexity attention mechanism for netlist encoding, enabling LLMs to make sizing decisions from a global perspective. Third, it integrates a differentiable Static Timing Analysis (STA) engine to refine LLM-predicted gate size probabilities by directly optimizing Total Negative Slack (TNS) through gradient descent. Experimental results on 5 unseen million-gate industrial designs in a commercial 3nm node show that LEGO-Size achieves up to 125x speed up with 37% TNS improvement over an industry-leading commercial signoff tool with minimal power and area overhead.

Modeling the effect of coupling-noise on circuit delay is a key issue in static timing analysis and involves thevictim-aggressor alignmentproblem. As delay-noise strongly depends on the skew between the victim-aggressor driver input transitions, it is not possiblea prioriidentify the victim-driver input transition that results in the worst-case delay-noise. Several approaches have been proposed in literature which heuristically search for the worst-case victim-aggressor alignment. This paper presents an analytical result that obviates the need to search for theoptimalvictim-driver input transition, thereby simplifying the victim-aggressor alignment problem significantly. Using the properties of standard nonlinear complementary metal-oxide semiconductor drivers, it is shown that for monotonic input transitions the worst-case victim-driver input transition is the one that switches at thelatestpoint in its timing window. Similarly, the victim-driver input alignment at the earliest point in the timing window is optimal for early-mode analysis. Although this result has been empirically observed in the industry, to the best of our knowledge this is the first paper which provides a rigorous analysis and shows that the above result holds for both linear and nonlinear drivers. It is also shown that the latest alignment of the victim-driver input transition results in the latest victimreceiver outputarrival time even for the cases where the victim is coupled tomultipleaggressors. Finally, experimental results show that limiting the alignment of the victim to only the latest victim-driver input transition can significantly reduce the runtime of existing approaches with no loss of accuracy.

Crosstalk delay-noise which occurs due to the simultaneous transitions of victim and aggressor drivers is very sensitive to their mutual alignment. Hence, during static noise analysis, it is crucial to identify the worst-case victim-aggressor alignment which results in the maximum delay-noise. Although several approaches have been proposed to obtain the worst-case aggressor alignment, most of them compute only the worst-case stage delay of the victim. However, in reality it is essential to compute the worst-case combined delay of victim stage and victim receiver gate [5, 9]. We propose a heuristic approach to compute the worst-case aggressor alignment which maximizes the victim receiver output arrival time. In this work, we use a novel cumulative gate overdrive voltage (CGOV ) metric to model the victim receiver output transition. HSPICE simulations, performed on industrial nets to validate the proposed methodology, show an average error of 1.7% in delay-noise when compared to the worst-case alignment obtained by an exhaustive sweeping.

Process induced variations in the interconnect capacitance and resistance have resulted in significant uncertainly in the interconnect delay. In this work, we propose a new method to compute the interconnect corner considering coupling-noise due to simultaneous switching of aggressors. In prior approaches, the interconnect corners were computed under the assumption that the aggressor nets are not switching and no coupling-noise is injected on the victim net. In this paper, we first show that the interconnect corners obtained under such assumptions could in reality be much different from the true interconnect corner and could therefore result in optimistic delay analysis, particularly for fast-path analysis performed to check hold time violations. We also show that in some cases, the interconnect corner may not lie at an extreme point of the process variation range. In this work, we use the Elmore delay metric to efficiently search for the correct interconnect corner of the victim stage considering delay noise. We then show experimental results to verify the effectiveness of our proposed approach and demonstrate that the traditional approaches of computing the interconnect corners could lead to errors of up to 60% on a net by net basis.

Increasing process variation in the nanometer regime motivates the use of statistical static timing analysis tools for timing verification. As device dimensions get smaller, signal integrity effects such as crosstalk noise become more significant. Therefore, it is necessary to accurately model the impact of crosstalk noise on the circuit delay. Process variations cause variability in the crosstalk alignment which leads to the variability in the delay noise. However, most of the existing approaches model delay noise as a worst-case deterministic quantity. In this work, we capture the variability of delay noise by first deriving the closed-form expressions of mean and standard deviation of the delay noise distribution. Next, we obtain the correlation information of the delay noise and use it to represent the delay noise distribution in canonical form. Delay noise, in canonical form, can easily be integrated with existing SSTA tools. We show experimental results that verify the accuracy of our approach.

We present, in this paper, novel algorithms to compute the set of "top-k" aggressors in a design. We show that the computation of the set of top-k aggressors is non-trivial, since we must consider all permutations of aggressors that are coupled to a critical path. Also, different sets of aggressors contribute different amounts of noise to each critical path and a brute-force enumeration to obtain the set of top-k aggressors has impractical runtime. Our proposed approach uses two key techniques to reduce the runtime complexity: Firstly, we model the delay noise propagated from a victim net to its fanout net by a so-called pseudo aggressor, which simplifies our problem formulation significantly. Secondly, we define a dominance property for aggressor sets, which imposes a partial ordering on the aggressor sets and allows us to efficiently prune the enumeration space. We then demonstrate the effectiveness of our proposed algorithm on benehmark circuits.

Modeling the effect of coupling noise on circuit delay is a key issue in static timing analysis (STA) and involves the “victimaggressor alignment” problem. As delay-noise depends strongly on the skew between the victim-aggressor input transitions’, it is not possible to apriori identify the victim input transition that results in the latest arrival time at the victim. Several approaches that heuristically search for the worst-case victim-aggressor alignment have been proposed in literature. In this paper we present an analytical result that obviates the need to search for the worst-case victim input transition, thereby simplifying the victim-aggressor alignment problem significantly. Using the properties of standard nonlinear CMOS drivers, we show that regardless of the switching of the aggressors, the worst-case victim input transition is the one that switches at the latest point in its timing window. Although this result has been empirically observed in the industry, to the best of our knowledge, this is the first work that provides a rigorous analysis and shows that the result holds for both linear and non-linear drivers. We also show that limiting the alignment of the victim to only the latest victim input transition can significantly reduce the runtime of existing heuristic techniques with no loss of accuracy.