The performance of a vector processor accessing vectors placed in memory is strongly dependent on the conflicts produced in the memory subsystem. These conflicts delay the task of the functional units. There can be conflicts between elements of the same vector and between elements of different vector streams. It is known that the presence of the last kind of conflicts is the main cause of cycles lost. This paper proposes an order to access the elements of a vector stream that reduces the average memory access time in vector processors when several vector streams are concurrently accessed. The proposed order determines that the memory system observes the same stride for all the vector streams of a stride family. Conflicts between concurrent vector streams of the same family are completely eliminated if the rate at which memory modules are requested is less than or equal to their service rate. For other cases, the number of lost cycles due to conflicts is dramatically reduced.

In vector processors, the concurrent memory access of several vector streams causes inter-conflicts between references.In a complex memory system where several memory modules are mapped in every bus the number of conflicts increases because the bus must be shared by vector streams.In addition to the memory module access conflicts, bus access conflicts can appear, and also couplings of both type of conflicts.This paper proposes an access order to the vector elements and a mapping model of memory modules in buses that reduce the inter-conflicts in the steady-state.

In multivector processors, the lost cycles due to conflicts between concurrent vector streams make the effective throughput be lower than the peak throughput. When the request rate of all the concurrent vector streams to every memory module is less than or equal to the service rate, conflicts appear because concurrent vector streams reference memory modules in different orders. In addition, in a memory system where several memory modules are mapped in every bus (complex memory system) bus conflicts are added to memory module conflicts. This paper proposes an access order to the vector stream elements that reduces the average memory access time in vector processors with complex memory systems. When request rate is greater than the service rate, the proposed order reduces the numbe of lost cycles, and the effective throughput increases. In other cases, the effective throughput reach the peak throughput. The proposed order generates the memory references in such a way that the memory modules shared by the concurrent self-conflict-free vector streams, and the sections where memory modules are mapped, are referenced using the same order.