Context switching is both a highly utilized and highly repetitive routine in interrupt-driven systems, such as safety-critical control systems. Conventional context switching routines are sequential and dependent on data memory access, which may be detrimental to time-predictability. This publication explores the use of stacked register files for efficient and predictable context switching. Two complementary microarchitectures are characterized: combinationally addressed register windowing, and a novel parallel context stack (PCS). Both implementations enable minimal latency and inherent predictability in context switching. To efficiently utilize the benefit of stacked register files while limiting hardware costs, the heterogeneous interrupt (HETI) architecture is proposed. HETI integrates a small stacked register file for accelerating a dynamically selected subset of high-priority interrupts. Automatic firmware generation is contributed to enable seamless utilization of the HETI architecture. A total of four HETI configurations on an open-source RISC-V microcontroller are evaluated against the baseline platform and an implementation of Cortex-M style hardware-assisted stacking. Implementations on a TSMC 22nm technology demonstrate low area overhead for small HETI configurations and favorable frequency characteristics against the hardware-assisted stacking implementation. A representative layout of the full system with a HETI-4 instance is presented with a gate count overhead of 1.2% and no frequency detriment in relation to the baseline design. The functional performance evaluated in a synthetic case study demonstrates how the HETI design can reduce retired instruction count by up to 26% and allow for 21% more sleep in comparison to the software baseline and Cortex-M style solution, promising significant improvements to real-time response and energy efficiency.

The recent trend towards open architectures and open source hardware enables agile development of domain specific architectures. In this paper, we explore and propose the design and implementation of AnTiQ, a hardware-accelerated priority queue tailored to the needs of timer queue implementations and other cases where removal of arbitrary elements, a feature we found lacking in related work, is desirable. The key novelty of AnTiQ is the arbitrary remove or DROP operation, which along with PUSH, POP and PEEK is performed in constant time. The design was conceived by reviewing existing implementations of hardware priority queues and analysing the fundamental characteristics of three queue architectures: the shift register queue, the systolic array queue and the binary heap queue. The systolic array architecture was chosen for our design due to its pipelined structure and ability to provide constant time responses to queue operations regardless of the queue depth. The architecture and implementation of our RTL prototype is presented and relevant behavioural corner cases in the design are identified. The implementation of our design achieved a clock frequency of 350 MHz on a Xilinx VCU 118 FPGA. The scalability of the design is evaluated through FPGA synthesis for 32, 64, 128 and 256 depth configurations and compared to the related work. We elaborate on directions for further development and future work towards monotonic timer implementations for the RTIC framework, a domain specific Rust language extension for concurrent programming targeting bare metal microcontrollers.

Memory safety is instrumental to the safety and security of software systems. The Rust language stands out with a type system and underlying memory model targeting memory safety without the need for dynamic garbage collection, making Rust a viable option for embedded applications. In this paper we present an integrated tool for call-stack analysis of Rust applications. We cover both theoretical and practical challenges, their solutions and open questions. The cargo-call-stack tool is useful for analyzing Rust applications in general, and embedded Rust in particular. To the latter, we show that using the call-stack analysis we can give guarantees of total memory safety, free of assumptions on operating systems and underlying memory protection mechanisms in hardware. The feasibility of the approach is demonstrated by applying the `call-stack' tool on production code targeting a light-weight ARM Cortex-M platform.

Symbolic execution allows us to observe and assert properties of program code executing under (partially) unknown inputs and state. In this work we present a case study demonstrating that safety functions implemented in the Rust programming language can be verified by an assertion based approach. To this end, we leverage on previous developments adopting LLVM-KLEE for symbolic execution of Rust programs.In particular we show that reliability can be ensured by proven absence of undefined behavior and that safety properties (expressed as assertions) can be ensured for all reachable paths of the underlying implementation (under symbolic inputs). Moreover, the verification (besides stating assertions) is fully automatic and can be applied without any changes made to the implementation. While assertions have the advantage of being familiar to the mainstream programmer, they lack the expressiveness of dedicated logic developed for model checking. The paper also discusses complexity issues arising from path/state explosion inherent to symbolic execution. The feasibility of the approach is demonstrated on a representative use case implementing a safety function (equality) from the PLCopen library. We obtain complete path- (466) and state- (8) coverage in under 2 seconds for the given example on an i7-7700 laptop computer.

C programming dominates the mainstream of embedded development as of today. To aid the development, hardware abstractions, libraries, kernels, and light-weight operating systems are commonplace. However, these typically offer little or no help to automatic worst-case execution time (WCET) estimation, and thus manual test and measurement based approaches remain the de facto standard. For this paper, we take the outset from the Real-Time For the Masses (RTFM) framework, which is developed to facilitate embedded software development for IoT devices and provides highly efficient implementations, suitable to the mainstream of embedded system design. Although the Rust language plays currently a minor part in embedded development, we believe its properties add significant improvements and thus implement our RTFM framework in Rust. We present an approach to worst-case execution time estimation in the context of RTFM tasks and critical sections, which renders sufficient information for further response time and schedulability analysis. We introduce our test bench, which utilizes the KLEE tool for automatic test vector generation and subsequently performs cycle accurate hardware-in-the-loop measurements of the generated tests. The approach is straightforward and fully automatic. Our solution bridges the gap in between measurement based and static analysis methods for WCET estimation. We demonstrate the feasibility of the approach on a running example throughout the paper and conclude with a discussion on its implications and limitations.

The Rust language stands out with a type system and underlying memory model targeting memory safety. The accompanying rustc compiler is typically able to statically prove the safety conditions and accept or reject input programs accordingly. However, e.g., cases of raw array indexing are in general out of reach for static analysis and promoted to runtime verification rendering executables with partial correctness guarantees (aborting with a panic on safety violations). For safety-critical applications, this requires proper panic handling, which is by itself a hard problem. Moreover, runtime verification may be undesirable for performance reasons and hence calling for stronger methods to static program analysis. In this paper, we take the approach of symbolic execution and propose a generic contract based verification process for programs written in Rust. For the verified properties (assertions), the program is both safe and panic free. Besides correctness, this implies further performance improvements as code for runtime verification can be safely dropped. We demonstrate the feasibility of the approach by adopting the KLEE symbolic execution engine to analyze LLVM bitcode extracted from Rust programs and libraries under verification and discuss its implications and limitations.

Dynamic memory management is typically implemented using a global memory allocator, which may negatively impact the performance, reliability, and predictability of a program; in effect standards around safety-critical applications often discourage or even disallow dynamic memory management. This paper presents heapless, a collection of dynamic data structures (for vectors, strings, and circular buffers) that can be either stack or statically allocated, thus free of global allocator dependencies. The proposed data structures for vectors and strings closely mimic the Rust standard library implementations while adding support to gracefully handling cases of capacity exceedance. Our circular buffers act as queues and allowing channel like usage (by splitting). The Rust memory model together with the ability of local reasoning on memory requirements (brought by heapless) facilitates establishing robustness/safety guarantees and minimize attack surfaces of (industrial) IoT systems. We show that the heapless data structures are highly efficient and have predictable performance, thus suitable for hard real-time applications. Moreover, in our implementation heapless data structures are non-relocatable allowing mapping to hardware, useful, e.g., to DMA transfers. The feasibility, performance, and advantages of heapless are demonstrated by implementing a JSON serialization and de-serialization library for an ARM Cortex-M based IoT platform.

The IEC 61499 standard provides means to specify distributed control systems in terms of function blocks. For the deployment, each device may hold one or many logical resources, each consisting of a function block network with service interface blocks at the edges. The execution model is event driven (asynchronous), where triggering events may be associated with data (and seen as messages). In this paper, we propose a low-complexity implementation technique allowing to assess end-to-end response times of event chains spanning over a set of networked devices. Based on a translation of IEC 61499 to RTFM11Real-time for the masses.

Engineering and computer science have come up with a variety of techniques to increase the confidence in systems, increase reliability, facilitate certification, improve reuse and maintainability, improve interoperability and portability. Among them are various techniques based on formal models to enhance testing, validation and verification. In this paper, we are concentrating on formal verification both at runtime and design time of a system. Formal verification of a system property at design time is the process of mathematically proving that the property indeed holds. At runtime, one can check the validity of the property and report deviations by monitoring the system execution. Formal verification relies on semantic models, descriptions of the system and its properties. We report on ongoing verification work and present two different approaches for formal verification of IEC 61499-based programs. We provide two examples of ongoing work to exemplify the design and the runtime verification approaches.

Concurrent programming is dominated by thread based solutions with lock based critical sections. Careful attention has to be paid to avoid race and deadlock conditions. Real-Time for The Masses (RTFM) takes an alternative language approach, introducing tasks and named critical sections (via resources) natively in the RTFM-core language. RTFM-core programs can be compiled to native C-code, and efficiently executed onto single-core platforms under the Stack Resource Policy (SRP) by the RTFM-kernel. In this paper we formally define the well-formedness criteria for SRP based resource management, and develop a certified (formally proven) implementation of the corresponding compilation from nested critical sections of the input RTFM-core program to a resulting flat sequence of primitive operations and scheduling primitives. Moreover we formalise the properties for resource ceilings under SRP and develop a certified algorithm for their computation. The feasibility of the described approach is shown through the adoption of the Why3 platform, which allows the necessary verification conditions to be automatically generated and discharged through a variety of automatic external SMT-solvers and interactive theorem provers. Moreover, Why3 supports the extraction of certified Ocaml code for proven implementations in WhyML. As a proof of concept the certified extracted development is demonstrated on an example system.

Embedded systems for critical applications are typically specified with requirements on predictable timing and safety. While ensuring predictable timing, the RTFM-lang (Real-Time For the Masses) model of computation (MoC) currently lacks memory access protection among real-time tasks. In this paper, we discuss how to safely verify task execution given a specification using the RTFM-MoC. Furthermore, an extension to the RTFM-core infrastructure is outlined and tested with use cases of embedded development. We propose a method for run time verification exploiting memory protection hardware. For this purpose, we introduce memory resources to the declarative language RTFM-core allowing compliance checks. As a proof of concept, compiler support for model analysis and automatic generation of run time verification code is implemented together with an isolation layer for the RTFM-kernel. With this verification foundation, functional run time checks as well as further overhead assessments are future research questions.

The IEC 61499 standard proposes an event driven execution model for component based (in terms of Function Blocks), distributed industrial automation applications. However, the standard provides only an informal execution semantics, thus in consequence behavior and correctness relies on the design decisions made by the tool vendor. In this paper we present the formalization of a subset of the IEC 61499 standard in order to provide an underpinning for the static verification of Function Block models by means of deductive reasoning. Specifically, we contribute by addressing verification at the component, algorithm, and ECC levels. From Function Block descriptions, enriched with formal contracts, we show that correctness of component compositions, as well as functional and transitional behavior can be ensured. Feasibility of the approach is demonstrated by manually encoding a set of representative use-cases in WhyML, for which the verification conditions are automatically derived (through the Why3 platform) and discharged (using automatic SMT-based solvers). Furthermore, we discuss opportunities and challenges towards deriving certified executables for IEC 61499 models.

The IEC 61499 standard provides an executable model for distributed control systems in terms of interacting function blocks. However, the current IEC 61499 standard lacks appropriate timing semantics for the specification of timing requirements, reasoning on timing properties at the model level, and for the timing verification of a specific deployment. In this paper we address this fundamental shortcoming by proposing Real-Time-4-FUN, a real-time semantics for IEC 61499. The key property is the preservation of non-determinism, allowing us to reason on (and verify) timing properties at the model level without assuming any specific scheduling policy or stipulating specific order of execution for the deployment. This provides for a clear separation of concerns, where the designer can focus on properties of the application prior to, and separately from, deployment verification. The proposed timing semantics is backwards compatible to the current standard, thus allow for reuse of existing designs. The transitional property allows timing requirements to propagate to downstream sub-systems, and can be utilized for scheduling both at device and network level. Based on a translation to RTFM-tasks and resources, IEC 61499 models can be analyzed, compiled and executed. As a proof of concept the timing semantics has been experimentally implemented in the RTFM-core language and the accompanying (thread based) RTFM-RT run-time system.

The IEC 61449 standard provides an outset for designing and deploying distributed control systems. Recently, a mapping from IEC 61499 to the RTFM-kernel API has been presented. This allows predictable real-time execution of IEC 61499 applications on light-weight single-core platforms. However, integrating the RTFM-kernel (bare-metal runtime) into potential deployments requires developing device drivers, protocol stacks, and the like. For this presentation, we apply the mapping from IEC 61499 to the RTFM-MoC task and resource model implemented by the RTFM-core language. The compilation from RTFM-core can be targeted to both, RTFM-kernel and the introduced runtime system RTFM-RT. In this paper, we detail the generic RTFM-RT runtime architecture, which allows RTFM-core programs to be executed on top of thread based environments. Furthermore, we discuss our implementation regarding scheduling specifics of Win32 threads (Windows) and Pthreads (Linux and Mac OS X). Using our RTFM-RT implementation for deployment, predictable IEC 61499 execution together with access to abovementioned operating system functions are achieved. For further developments, we discuss the needed scheduling options to achieve hard real-time and analysis required to eliminate deadlocks.

The IEC 61499 standard provides means to specify distributed control systems in terms of function blocks. The execution model is event driven (asynchronous), where triggering events may be associated with data (and seen as a message). In this paper we propose a low complexity implementation technique allowing to assess end-to-end response time of event chains spanning over a set of networked devices. In this paper we develop a method to provide safe end-to-end response time taking both intra- and inter-device delivery delays into account. As a use case we study the implementation onto (single-core) ARM-cortex based devices communicating over a switched Ethernet network. For the analysis we define a generic switch model and an experimental setup allowing us to study the impact of network topology as well as 802.1Q quality of service in a mixed critical setting. Our results indicate that safe sub millisecond end-to-end response times can be obtained using the proposed approach.

The mainstream of embedded software development as of today is dominated by C programming. To aid the development, hardware abstractions, libraries, kernels and lightweight operating systems are commonplace. Such kernels and operating systems typically impose a thread based abstraction to concurrency. However, in general thread based programming is hard, plagued by race conditions and dead-locks. For this paper we take an alternative outset in terms of a language abstraction, RTFM-core, where the system is modelled directly in terms of tasks and resources. In compliance to the Stack Resource Policy (SRP) model, the language enforces (well-formed) LIFO nesting of claimed resources, thus SRP based analysis and scheduling can be readily applied. For the execution onto bare-metal single core architectures, the rtfm-core compiler performs SRP analysis on the model and render an executable that is deadlock free and (through RTFM-kernel primitives) exploits the underlying interrupt hardware for efficient scheduling. The RTFM-core language embeds C-code and links to C-object files and libraries, and is thus applicable to the mainstream of embedded development. However, while the language enforces well-formed resource management, control flow in the embedded C-code may violate the LIFO nesting requirement. In this paper we address this issue by lifting a subset of C into the RTFM-core language allowing arbitrary control flow at the model level. In this way well-formed LIFO nesting can be enforced, and models ensured to be correct by construction. We demonstrate the feasibility by means of a prototype implementation in the rtfm-core compiler. Additionally, we develop a set of running examples and show in detail how control flow is handled at compile time and during run-time execution.

Function Blocks provides a means to model and program industrial control systems. The recently acclaimed IEC 61499 standard allows such system models to be partitioned and executed in a distributed fashion. At device level, such models are traditionally implemented onto programmable logic controllers that underneath have an operating system and a software run-time environment which implies high resource demands. However, there is a current trend to involve small embedded systems (so called Internet of Things devices) integrated into such distributed control systems. To this end, we seek to address the outsets for real-time execution of Function Block based designs onto light-weight controllers (MCUs) with limited resources (memory and CPU). Furthermore, we propose a mapping of the Function Block execution semantics onto the RTFM-kernel, and discuss opportunities for off-line (design time) analysis with respect to response time, overall schedulability and memory requirements.

The number and complexity of networked sensors and actuators in industrial monitoring and control systems is rapidly increasing. This calls for flexible yet efficient methods (w.r.t. time and money) for designing, deploying and maintaining such systems. To this end, Service Oriented Architectures (SOAs) and wireless technologies are foreseen to play important roles. In the area of Wireless Sensor Networks (WSNs), TinyOS (TOS) has gained wide spread use, mainly because it offers a simple programming model. Moreover TOS comes with a ready made code base (e.g., protocol stacks needed to implement SOA enabled devices) and is available for a large number of light-weight target platforms. However, TOS has yet to make its way into industrial applications where real-time operation is required (which is typical to monitoring and control systems). As being designed primarily with simplicity in mind, the TOS execution model for tasks is non-preemptive, limiting system responsiveness and schedulability. To overcome this problem preemptive TOSThreads has been introduced. However, this introduces the additional complexity of traditional multi-thread programming, thus the main benefit of TOS is lost. In this paper we present an alternative execution model for TOS, that allows preemptive execution while preserving the simplicity of vintage TOS. We exemplify the impact of scheduling to a typical sensor/actuator node scenario. Our results indicate that the proposed preemptive execution model is capable of reducing both delay and drop rate for the given scenario.

Industrial process automation systems are adopting event based communication. Pushing control loops towards low-level devices implies a need for lightweight embedded devices that are able to recognize and to react to events. Atomic events however, such as a value read by an individual sensor exceeding certain value, do not separately suffice to capture scenarios where a reaction should occur to a sequence of low-level events matching certain pattern, rather than to a single atomic event. Therefore, it becomes desirable that resource-constrained low-level devices are equipped with some, possibly lightweight, form of event filtering and processing. In this paper we propose to implement a lightweight complex event processing using the concurrent reactive objects (CRO) model. A core feature of the CRO model is its s ability to react to atomic events. Between the reactions, which basically are function executions, the system remains idle, and thus does not occupy the CPU and is energy-efficient. Additionally, CRO models can be executed in an efficient and predictable manner onto resource constrained platforms and offers low-overhead real-time scheduling through exploiting underlying interrupt hardware according to given time constraints.

For the future we foresee each vehicle to feature wireless communication (to the Internet and/or other vehicles) over various technologies, e.g., UMTS/GPRS, and WLAN/WiFi. In this paper we show how access to such communication resources could be granted to individual components (CAN bus connected ECUs) in the car by allowing transparent data transport using the standardized Internet Protocol (IP). Our experiments show that a complete IP Over CAN implementation, providing both UDP and TCP transport over IP, running on an Atmel AT90CAN128 is capable of transfer speeds up to 200 kbits while using less than 2 kbytes of dynamic RAM.

Embedded systems are often operating under hard real-time constraints. Such systems are naturally described as time-bound reactions to external events, a point of view made manifest in the high-level programming and systems modeling language Timber. In this paper we demonstrate how the Timber semantics for parallel reactive objects translates to embedded real-time programming in C. This is accomplished through the use of a minimalistic Timber Run-Time system, TinyTimber (TT). The TT kernel ensures state integrity, and performs scheduling of events based on given time-bounds in compliance with the Timber semantics. In this way, we avoid the volatile task of explicitly coding parallelism in terms of processes/threads/semaphores/monitors, and side-step the delicate task to encode time-bounds into priorities. In this paper, the TT kernel design is presented and performance metrics are presented for a number of representative embedded platforms, ranging from small 8-bit to more potent 32- bit micro controllers. The resulting system runs on bare metal, completely free of references to external code (even C-lib) which provides a solid basis for further analysis. In comparison to a traditional thread based real-time operating system for embedded applications (FreeRTOS), TT has tighter timing performance and considerably lower code complexity. In conclusion, TinyTimber is a viable alternative for implementing embedded real-time applications in C today.

Designing a garbage collector with real-time properties is a particularlydifficult task, involving the construction of both an incremental run-timealgorithm as well as methods enabling a priori reasoning about schedulability in two dimensions (time and memory usage in conjunction). In order to comply with such ambitious goals with any amount of formal rigor, a comprehensive understanding of the actual algorithm used is of course a fundamental requirement. In this paper we present a formal model of an incremental copying garbage collector, where each atomic increment is modeled as a transition between states of a heap process. Soundness of the algorithm is shown by proving that the garbage collecting heap process is weakly bisimilar to a non-collecting heap with infinite storage space. In addition, we show that our collector is both terminating and useful, in the sense that it actually recovers the unreachable parts of any given heap in a finite number of steps.

Wireless sensor nodes are a versatile, general-purpose technology capable of measuring, monitoring and controlling their environment. Even though sensor nodes are becoming ever smaller and more power efficient, there is one area that is not yet fully addressed; power supply units (PSUs). Standard solutions that are efficient enough for electronic devices with higher power consumption than sensor nodes, such as mobile phones or PDAs, may prove to be ill suited for the extreme low-power and size requirements often found on wireless sensor nodes. In this paper, a system-level design of power management architecture (PMA) is presented. The PMA is an integration of PSU hardware and various software components, and is capable of supplying a sensor node with energy from multiple sources, as well as providing status information from the PSU. The heart of the architecture is a context- and power-aware task manager, which controls when the nodes low-power modes are activated, and is highly integrated with PSU hardware as well as other software components in the system. Its main responsibility is to schedule when energy consuming tasks can be dispatched. Depending on the task priority and system configuration, a task can be dispatched, discarded or delayed. This approach ensures that only critical tasks will be allowed to use the battery, and that the system will be powered by renewable energy when performing other non-critical tasks.

Abstract — Bluetooth-equipped wireless sensor nodes can be quickly integrated in small home networks. These networks can be utilized e.g. for surveillance, home monitoring and automation. Accurate time is an important factor for time-stamping of sensor data, encryption/authentication and it can also to used to implement time synchronous schemes for low power radio communication. We argue that IP-based time synchronization, such as various flavors of the NTP protocol, can be used with Bluetooth networks. This in combination with an activation schedule allows an efficient trade-off between energy consump-tion and communication delay, and provides easy integration with available infrastructure. The proposed approach in this paper is well suited for smaller wireless home networks, typically single-hop networks with access points that are always available. Our approach is verified by experiments performed on a COTS-based platform using Bluetooth. I.

Abstract—Emerging wireless communication standards and more capable sensors and actuators have pushed further development of wireless sensor networks. Deploying a large number of sensor nodes requires a high-level framework enabling the devices to present themselves and the resources they hold. The device and the resources can be described as services, and in this paper, we review a number of well-known service discovery protocols. Bonjour stands out with its auto-configuration, distributed architecture, and sharing of resources. We also present a lightweight implementation in order to demonstrate that an emerging standards-based device and service discovery protocol can actually be deployed on small wireless sensor nodes. Index Terms: Service discovery, wireless sensor, sensor networks.

The minimization of power consumption is an important design constraint for circuits used in portable devices. The s itching activity of a circuit node in a CMOS digital circuit directly contributes to overall power dissipation. By approximating the switching activity of circuit nodes as internal switching probabilities in Binary Decision Diagrams BDDs), it is possible to estimate the dynamic power dissipation characteristic of circuits resulting from a structural mapping of a BDD. A technique for minimizing the overall sum of switching probabilities is presented. The method is based on efficient local operations on a BDD representing the functionality of the circuit to be realized. The resulting circuit that is obtained by mapping the BDD to CMOS Pass Transistors has in simulation using a commercially available process model) shown reduced power dissipation characteristic. Experimental results on a set of MCNC benchmarks are given for this technique.

The introduction of Decision Diagrams (DDs) has brought new means towards solving many of the problems involved in digital circuit design. Compactness of the representation is one key issue. Ordered Pseudo Kronecker Decision Diagrams (OPKDDs) together with the use of complemented edges is known to offer the most general ordered read-once DD representation at the bit-level, hence OPKDDs hold all minimal sized bit-level ordered DDs for a given function. This representation allows us to trade-off diagram canonicity against compactness. Ternary-OPKDDs (TOPKDDs) implicitly holds all OPKDDs for a given variable order. We state the canonicity criteria for TOPKDDs having complemented edges and develop an efficient sifting based method for their minimization. Furthermore, a heuristic minimization algorithm for OPKDDs is devised, utilizing the redundancies of Ternary-OPKDDs (TOPKDDs). Experiments on a set of MCNC benchmarks confirm the potential compactness of OPKDDs and demonstrate the efficiency of the proposed heuristics.

The design process of digital circuits is often carried out in individual steps, like logic minimization, mapping and routing. This leads to quality loss, e.g. in cases where highly optimized netlists fit badly onto the target architecture. Lattice diagrams have been proposed as one possible solution. They offer a regular two dimensional structure, thus overcoming the routing problem. However elegant, presented methods have only been shown to find practical lattice representations for small functions. We present heuristic synthesis methods for Pseudo-Symmetric Pseudo Kronecker Decision Diagrams (PSP-KDDs) applicable to incompletely specified multiple output functions. The lattice structure maps directly to both ASICs and fine grain FPGAs. Our method (combining logic minimization, mapping and routing) seeks to minimize area and delay by heuristic methods. Experimental results on a set of MCNC benchmarks show superior quality to previous methods and in many cases even optimal depth results for unfolded lattices.

Dynamic synchronous transfer mode (DTM) is a broadband network architecture based on fast circuit-switching augmented with dynamic reallocation of resources. It provides a service based on multicast, multirate channels with short setup delay and supports applications with real-time requirements on quality of service as well as applications with bursty, asynchronous traffic. The paper describes the DTM architecture and its distributed resource management scheme. Performance analysis results from network simulations are presented. The analysis is performed with respect to throughput and access delay for two network topologies: a dual bus and a grid of dual buses. The effects of varying user requirements, internode distances and transfer size are studied for uniform traffic patterns. The results indicate that the overhead for establishing channels is low (a few hundred microseconds), which gives a high degree of utilization even for short transfers. The analysis also shows that when channels are established very frequently, the signaling capacity limits the performance.

No abstract available.