Integrated circuits operating in the near/subthreshold region offer low energy consumption. However, due to the constrained voltage scalability of SRAMs, efficient power delivery is difficult to achieve. A traditional implementation would require at least two distinct voltage supplies generated by possibly two power converters. In this article, a new implementation for near/subthreshold operation is presented. The proposed implementation consists of a new “converter-free” design based on a three-level voltage stack operating at 1.8 V ± 5%. Here, the leakage current from the SRAMs in the top stack is recycled to sustain the near/subthreshold operation of the logic circuits in the two lower stacks. A test chip with the proposed voltage-stacking technique was implemented in a 28-nm low- Vth (LVT) fully depleted silicon on insulator (FDSOI) technology. The test chip is an ultralow-power advanced system-on-chip (SoC) consisting of an RISC-V core, a coarse-grained reconfigurable accelerator, and peripherals. The SoC uses a current sink and an adaptive body-bias controller for voltage regulation of the intermediate voltage rails between the stacks. The proposed system achieves up to 95% power delivery efficiency with negligible area overhead (~ 1%). The silicon measurement shows that the system energy efficiency is improved by 1.6× on average, and the energy consumption is reduced by 37% on average compared to the flat implementation.

In this work, a design of an IEEE 802.15.4 con-formant O-QPSK demodulator is proposed, which is capable of trading off receiver sensitivity for power savings. Such design can be used to meet rigid energy and power constraints for many applications in the Internet-of-Things (IoT) context. In a Body Area Network (BAN), for example, the circuits need to operate with extremely limited energy sources, while still meeting the network performance requirements. This challenge can be addressed by the paradigm of adequate computing, which trades off excessive quality of service for power or energy using approximation techniques. Three different, adjustable approximation techniques are integrated into the demodulation to trade off effective signal quantization bit-width, filtering performance, and sampling frequency for power. Such approximations impact incoming signal sensitivity of the demodulator. For detailed trade-off analysis, the proposed design is implemented in a commercial 40-nm CMOS technology to estimate power and in Python to estimate sensitivity. Simulation results show up to 64% power savings by sacrificing $\tilde 7$ dB sensitivity.

On the trend of ultrasound-based gesture recognition, this study introduces the concept of time-sequence classification of ultrasonic patterns induced by hand movements on a microphone array. We refer to time-sequence ultrasound echoes as continuous frequency patterns being received in real-time at different steering angles. The ultrasound source is a single tone continuously being emitted from the center of the microphone array. In the interim, the array beamforms and locates an ultrasonic activity (induced echoes) after which a processing pipeline is initiated to extract band-limited frequency features. These beamformed features are organized in a 2D matrix of size 11 × 30 updated every 10ms on which a Temporal Convolutional Network (TCN) outputs continuous classification. Prior to that, the same TCN is trained to classify Doppler shift variability rate. Using this approach, we show that a user can easily achieve 49 gestures at different steering angles by means of sequence detection. To make it simple to users, we define two Doppler shift variability rates; very slow and very fast which the TCN detects 95-99% of the time. Not only a gesture can be performed at different directions but also the length of each performed gesture can be measured. This leverages the diversity of inair ultrasonic gestures allowing more control capabilities. The process is designed under low-resource settings; that is, given the fact that this real-time process is always-on, the power and memory resources should be optimized. The proposed solution needs 6.2 - 10.2 MMACs and a memory footprint of 6KB allowing such gesture recognition system to be hosted by energy- constrained edge devices such as smart-speakers.

Fully depleted silicon on insulator (FDSOI) is attractive for its low cost and low power; the mixed-Vt and body-bias levers that it affords expand the performance-power solution space. However, in FDSOI, different-Vt (i.e., low Vt and regular Vt) devices must be isolated from each other, which makes realization of fine-grained mixed-Vt/body-biasing in layout extremely challenging. In this article, we study heuristic methods aimed at exploitation of fine-grained mixed-Vt in FDSOI implementation. We propose a novel speed domain partitioning (SDP) problem formulation that comprehends the spatial contiguity restrictions arising from flip-well structure of low Vt regions in popular 28-nm commercial FDSOI offerings. We explore a wide space of implementation flows that include an integer linear programming (ILP)-based approach, and a heuristic (sensitivity-based) optimization. Our experimental studies have been performed across multiple commercial enablements. We observe that outcomes are library- and design-dependent. For implementations using generic library options, up to 20% speed improvement with 54% low Vt region is seen for one out of four testcases studied. For implementations using “rich” library options, up to 7% speed improvement with 26% low Vt region is achieved. We provide a discussion that summarizes root-cause, intrinsic difficulties of fine-grained exploitation of mixed-Vt. Finally, we suggest a “decision tree” to help assess a design's amenability to fine-grained mixed-Vt implementation, and to help guide design flow selection for better design QoR.

Tracking the gradual effect of silicon aging requires fine-grain slack monitoring. Conventional slack monitoring techniques intend to measure worst-case static slack, i.e. the slack of longest timing path. In sharp contrast to the conventional techniques, we propose a novel technique that is based on dynamic excitation of in-situ delay monitors, i.e. dynamic excitation of the timing paths that are monitored. As the delays degrade, the path delays increase and the monitors are excited more frequently. With the proposed technique, a fine-grained signature of the delay degradation is extracted from the excitation rate of monitors.

To handle the rigid power and energy constraints in the Digital BaseBand (DBB) of Wireless Sensor Networks (WSN)s, we introduce approximate computing as a new power reduction method. The Received Signal Strength Indicator (RSSI) computation is a key element in DBB processing. We evaluate the trade-off in RSSI computation between Quality-of-Service (QoS) and power consumption through circuit-level approximation. RSSI elements are approximated in such a way that error propagation is minimized. In an industrial 40-nm CMOS technology, substantial energy savings up to 24% are achieved for every successfully transferred bit in DBB processing in a low- power listening WSN scenario.

With the increasing demand on voice recognition services, more attention is paid to simpler algorithms that are capable to run locally on a hardware device. This paper demonstrates simpler speech features derived in the time-domain for Keyword Spotting (KWS). The features are considered as constrained lag autocorrelations computed on overlapped speech frames to form a 2D map. We refer to this as Multi-Frame Shifted Time Similarity (MFSTS). MFSTS performance is compared against the widely known Mel-Frequency Cepstral Coefficients (MFCC) that are computed in the frequency-domain. A Temporal Convolutional Network (TCN) is designed to classify keywords using both MFCC and MFSTS. This is done by employing an open source dataset from Google Brain, containing ~ 106000 files of one-second recorded words such as, 'Backward', 'Forward', 'Stop' etc. Initial findings show that MFSTS can be used for KWS tasks without visiting the frequency-domain. Our experimental results show that classification of the whole dataset (25 classes) based on MFCC and MFSTS are in a very good agreement. We compare the performance of the TCNbased classifier with other related work in the literature. The classification is performed using small memory footprint (~ 90 KB) and low compute power (~ 5 MOPs) per inference. The achieved classification accuracies are 93.4% using MFCC and 91.2% using MFSTS. Furthermore, a case study is provided for a single-keyword spotting task. The case study demonstrates how MFSTS can be used as a simple preprocessing scheme with small classifiers while achieving as high as 98% accuracy. The compute simplicity of MFSTS makes it attractive for low power KWS applications paving the way for resource-aware solutions.

I. VLSI Systems: A Glance Into The Last Decades Since their inception in 1970s, VLSI systems have enabled several new technological capabilities and made them accessible to an unceasingly wider range of users, reaching a scale that has been exponentially increasing over the decades[1](seeFig. 1). Relentless integration of more complex systems has driven such remarkable evolution, as made possible by the inexorable miniaturization. As shown inFig. 1, more functionality has been crammed in a consistently smaller form factor, as exemplified by the physical volume shrinking of computers by 100 X/decade[2],[3]. At the same time, the energy per task has been decreasing at 10–100 X/decade, as shown inFig. 2, for several systems and system-on-chip subsystems[4]. This allowed packing more capabilities into the same power envelope, as generally observed in the electronic systems, even before the advent of the integrated circuit[5].

In this paper, a timing speculation technique with low-overhead in situ delay monitors placed along critical paths is presented. The proposed insertion of monitors enables timing error prevention within the same clock cycle. Compared to other techniques, the design cost per monitor in our technique is low because no additional gates for the guard banding, inspection window generation, and short path extension are required. We benchmarked our approach on an ARM Cortex M0. The insertion strategy reduces the number of monitors by up to ~23×, power by ~5.5×, and area by ~2.8× compared to the traditional in situ monitoring techniques that insert monitors at the flipflops. The timing error correction uses a global clock stretching unit to prevent errors within one cycle. With the proposed error prevention technique, -.22% more delay variation is tolerated with a negligible energy overhead of less than ~1%.

In-situ delay monitoring is an advanced technique to monitor the robustness of digital circuits. Conventionally, in-situ delay monitors are inserted at the end-points of timing paths. To reduce the number of monitors and to increase their observability, intermediate points have been considered. In sharp contrast to these works, we propose a low overhead technique where the insertion points are selected along the timing paths such that timing violations can be predicted without false negative detections. With our approach, the number of required monitors is reduced by up to 11X compared to end-point insertion techniques. The observability to delay degradation is 8X better with our approach, compared to techniques with straight monitor placement at intermediate points.

Pulsed-latches emerge as an ideal sequencing element for low power digital circuit design, serving as an alternative of flip-flops. In this paper, low power multi-bit pulsed-latches are proposed to construct pipeline stages in synchronous digital circuits. A method of integrating the proposed multi-bit pulsed-latches in the commercial design flows is also introduced. With the multi-bit pulsed-latches, up to 45% power savings are achieved for a variety of ITC benchmark circuits and an ARM Cortex-M0 as compared to the flip-flop based designs in an industrial 28-nm FDSOI CMOS technology. Furthermore, the power consumption of the clock distribution network and the layout area are reduced by up to 83% and 16%, respectively, with the proposed multi-bit pulsed-latches as compared to the flip-flop based designs.

Timing errors that are caused by the timing violations of sensitized circuit paths, have emerged as an important threat to the reliability of synchronous digital circuits. To protect circuits from these timing errors, designers typically use a conservative timing margin, which leads to operational inefficiency. Existing adaptive approaches reduce such conservative margins by predicting the timing errors in advance and adjusting the timing margin adaptively. However, these error prediction approaches overlook the impact of input workload (i.e., operands) on path sensitization, thereby resulting in a loss of accuracy. The diversity of input operands leads to complex path sensitization behaviors, making them hard to represent in timing error modeling. In this paper, we propose CLIM, a cross-level workload-aware timing error prediction model for functional units (FUs). CLIM predicts whether there are timing errors in FU at two levels: bit-level and value-level. At the bit level or value level, CLIM predicts each output bit or entire output value as one of two classes: {timing correct, timing erroneous} as a function of input workload and clock period, respectively. We apply supervised learning methods to construct CLIM, by using input operands, computation history and circuit toggling as input features, as well as outputs' timing classes as labels. These training data are collected from gate-level simulations (GLS) of post place-and-route designs in TSMC 45nm process. We evaluate CLIM prediction accuracy for various FUs and compare it with baseline models. On average, CLIM exhibits 95 percent prediction accuracy at value-level, 97 percent at bit-level, and executes at a rate 173X faster than GLS. We utilize CLIM to analyze the value-level and bit-level reliability of FUs under random and real-world application workloads. At value-level, CLIM-based reliability estimation is within 2.8 percent deviation on average of detailed GLS ground truth. At bit-level, we introduce the concept of bit-level reliability specification of error-tolerant applications and compare this with the CLIM-based bit-level reliability estimation. By comparison, CLIM will classify the application quality into two classes: {acceptable, non-acceptable}. On average, 97 percent application quality classification is consistent with GLS ground truth.

Energy and battery lifetime constraints are critical challenges to IC designs. Stacked power-domain implementation, which stacks voltage domains in a design, can effectively improve the power delivery efficiency and thus improve battery lifetime. However, such an approach requires balanced current between different domains across multiple operating scenarios. Furthermore, level shifter insertion (together with shifters' delay impacts), along with placement constraints imposed by power domain regions, can incur power and area penalties. To our knowledge, no existing work performs sub-block-level partitioning optimization for stacked-domain designs. In this paper, we present an optimization framework for stacked-domain designs. Based on an initial placement solution, we apply a flow-based partitioning that is aware of multiple operating scenarios, cell placement, and timing-critical paths to partition cells into two power domains with balanced current and minimized number of inserted level shifters. We further propose heuristics to define regions for each power domain so as to minimize placement perturbation, as well as a dynamic programming-based method to minimize the area cost of power domain generation. In an updated floorplan, we perform matching-based optimization to insert level shifters with minimized wirelength penalty. Overall, our method achieves more than ~10% and 3X battery lifetime improvements in function and sleep modes, respectively.

Future IoT systems are tightly constraint by cost and size and will often be operated from an energy harvester's output. Since these batteryless systems operate on intermittent energy they have to be able to retain their state during the power outages in order to guarantee computation progress. Due to the lack of large energy buffers the state needs to be saved quickly using residual energy only. In related work, the state is retained in-place by replacing all flip-flops with state retentive flip-flops (SRFF), which are powered by auxiliary supplies for retention or incorporate non-volatile memory cells. However, these SRFFs increase the power consumption during active operation impairing the overall systems efficiency. In this paper, we present a scan-chain based state retention approach, where the state is moved to memory using only 4.5pJ/b. Since our approach does not introduce any power overhead, this energy cost pays off after an on-time of just 100us compared to state-of-the-art in-place solutions. Moreover, compared to a software mechanism, our approach requires 6.6x less energy to move the state and is 5.8x faster.

Energy and battery lifetime constraints are critical challenges to IC designs. Stacked power-domain implementation, which connects voltage domains in series, can effectively improve power delivery efficiency and thus improve battery lifetime. However, such an approach requires balanced currents between different domains across multiple operating scenarios. Furthermore, level shifter insertion, along with placement constraints imposed by power domain regions, can incur significant power and area penalties. To the best of our knowledge, no existing work performs subblock-level partitioning optimization for stackeddomain designs. In this paper, we present an optimization framework for stacked-domain designs. Based on an initial placement solution, we apply a flow-based partitioning that is aware of multiple operating scenarios, cell placement, and timing-critical paths to partition cells into two power domains with balanced cross-domain current and minimized number of inserted level shifters. We further propose heuristics to define regions for each power domain so as to minimize placement perturbation, as well as a dynamic programming-based method to minimize the area cost of power domain generation. In an updated floor plan, we perform matching-based optimization to insert level shifters with minimized wirelength penalty. Overall, our method achieves an excellent current balance across stacked domains with less than 10% discrepancy, which results in up to more than 2× battery lifetime improvements.

Stacking voltage domains on top of each other is a design approach that is getting the attention of engineering communities due to the implicit high efficiency of the power delivery. Previous works have shown voltage stacking at the core level only. In this paper we present a more involved approach required to deploy voltage stacking not at the core level but at the IP level of a complex microcontroller. Our demonstrator chip features an ARM Cortex M0+ platform with an on-chip switched-capacitor voltage regulator. We chose to place the standard logic in one voltage domain between ground and VDD, and the memory "on top of it" between VDD and 2VDD, creating in this way a voltage stacked system. We further present silicon measurements that include a measured peak power efficiency in "stacked mode" of 96%.

Staying at the forefront of research, or in the top tier product market requires circuit innovation as a key differentiation. We are entering an era where more than Moore is becoming increasingly evident, not only because of the physical limitations of the technology but because of market diversity beyond PCs and servers. More than ever, application diversity marks the pace to differentiate by design not only by technology. In this paper we give insights on how circuit innovation continues to be key to making advancements in High Performance Mixed Signal systems.

There is much focus on timing error resilience for the speed critical paths of processors. In the context of growing parameter variations with technology scaling and voltage scaling, resilience helps to ensure functional correctness. Moreover it allows the chip to stretch its operating voltage and frequency beyond the conventional limits to meet the demand for high performance and low power. Conventionally, timing error resilience is achieved through variation tolerant circuitry at the cost of undesirable power, area and throughput overheads. Such overheads are aggravated by the presence of large number of critical timing paths in the design. In this paper, we propose a slack-aware timing margin redistribution technique for error resilience using time borrowing error avoidance flip-flops (EAFFs) while minimizing overheads. The proposed algorithm designs the processor critical paths ground up by inserting EAFFs at places where positive slack is available in the subsequent fan-out stage. Experiment results on an industrial processor design show that a timing margin improvement of 11% of the clock period can be achieved on 64% of the critical paths and a 55% timing margin on 45% of the critical paths without any throughput degradation. The area and power overheads of the additional flip-flops are 0.2% and 5.4%, respectively.

Resilient design techniques are used to (i) ensure correct operation under dynamic variations and to (ii) improve design performance (e.g., timing speculation). However, significant overheads (e.g., 16% and 14% energy penalties due to throughput degradation and additional circuits) are incurred by existing resilient design techniques. For instance, resilient designs require additional circuits to detect and correct timing errors. Further, when there is an error, the additional cycles needed to restore a previous correct state degrade throughput, which diminishes the performance benefit of using resilient designs. In this work, we describe an improved methodology for resilient design implementation to minimize the costs of resilience in terms of power, area, and throughput degradation. Our methodology uses two levers: selective-endpoint optimization (i.e., sensitivity-based margin insertion) and clock skew optimization. We integrate the two optimization techniques in an iterative optimization flow which comprehends toggle rate information and the trade-off between cost of resilience and margin on combinational paths. Since the error-detection network can result in up to 9% additional wirelength cost, we also propose a matching-based algorithm for construction of the error-detection network to minimize this resilience overhead. Further, our implementations comprehend the impacts of signoff corners (in particular, hold constraints, and use of typical vs. slow libraries) and process variation, which are typically omitted in previous studies of resilience trade-offs. Our proposed flow achieves energy reductions of up to 21% and 10% compared to a conventional (with only margin used to attain robustness) design and a brute-force implementation (i.e., a typical resilient design, where resilient endpoints are (greedily) instantiated at timing-critical endpoints), respectively. We show that these benefits increase in the context of an adaptive voltage scaling strategy.

In today's semiconductor industry we see a move towards smaller technology feature sizes. These smaller feature sizes pose a problem due to mismatch between identical cells on a single die known as local variation. In this paper a library tuning method is proposed which makes a smart selection of cells in a standard cell library to reduce the design's sensitivity to local variability. This results in a robust IC design with an identifiable behavior towards local variations. Experimental results performed on a widely used microprocessor design synthesized for a high performance timing show that we can achieve a timing spread reduction of 37% at an area increase cost of 7%.

For low-power digital ICs with ultra-wide voltage and frequency scaling (e.g., from the nominal supply voltage to the sub/near-threshold regime), achieving design closure can be a big challenge, especially when speed limits are pushed at very different voltages. This paper shares a practical logic synthesis recipe that helps to fulfill tight timing constraints. Our method includes: i) synthesizing circuits at a high voltage; ii) over-constraining maximal transition time; iii) pruning standard cell library based on cell delay degradation factor across voltages. This approach shows effectiveness on an industrial 90nm low-power micro-controller.

We discuss an adaptive fuzzy logic controller to accurately and robustly predict and track supply current variations of digital processors. The proposed controller tracks supply current variations without updating any parameter during its runtime prediction. It can be used to adjust the supply voltage and clock frequency of digital processors based on workload variations when accounting for timing-constraints and other practical requirements. Additionally, we comprehensively examine the stability analysis of the closed-loop configuration containing the fuzzy controller and the digital processor model. We prove that the fuzzy controller guarantees the asymptotic stability of the closed-loop architecture. Several experiments are performed to exhibit effectiveness of the proposed fuzzy controller comparing to the other existing conventional prediction methods. The results show that the proposed controller outperforms the other existing methods.

We present a design framework for wirelessly powered generic computing platforms that takes into account various system parameters in response to a time-varying energy source. These parameters are the charging profile of the energy source, computing speed (fclk), digital supply voltage (VDD), energy storage capacitance (Cs), and power conversion efficiency (η). We address both continuous and discrete operational modes of computation based on the energy source's charging profile. Unlike other reported works where investigations are limited to wireless energy transfer and functional demonstrations, our aim is to develop a theoretical model that comprises the complete system architecture by combining energy transfer and consumption in a step-by-step manner. We show that field resilience operation in a wireless energy field can be incorporated by modulating the power consumption in the digital platform in response to changing energy fields using this analysis. This paper also allows guidelines for choosing the appropriate computing policies based on the charging profile of energy source. This leads to an optimal, adaptive use of available energy in order to optimize the overall performance.

Process variability severely impacts the performance of circuits operating in the subthreshold domain. Among other reasons, this mainly stems from the fact that subthreshold current follows a widely spread Log-Normal distribution. In this paper we introduce a new transistor sizing methodology for standard cells. Our premise relies on balancing the N and P network currents based on statistical formulations. Our approach renders more robust cells. We observe up to 57% better performance and 69% lower energy consumption on a set of ISCAS circuits when they are synthesized with our library as opposed to a commercial library in a CMOS 90nm technology.

In this paper, we present a novel robust sliding-mode controller for stabilizing supply voltage and clock frequency of dual core processors determined by dynamic voltage and frequency scaling (DVFS) methods in the presence of systematic and random variations. We show that maximum rejection for process, voltage and temperature (PVT) variations can be achieved by using the proposed sliding-mode controller. The stabilization of the presented controller is confirmed by the Lyapanov method. Experimental results demonstrate maximum 20% robustness against 20% parameter variations for a hardware of two core processors executing a JPEG decoding application.

Worst-case design uses extreme process corner conditions which rarely occur. This limits maximum speed specifications and costs additional power due to area over-dimensioning during synthesis. We present a new design synthesis strategy for digital CMOS circuits that makes use of forward body biasing. Our approach renders consistently a better performance-per-area ratio by constraining circuit over-dimensioning without sacrificing circuit performance. An in-depth analysis of the body-bias-driven design theory is provided. It is complemented by an algorithm that enables fast reconstruction of the area-clock period tradeoff curve of the design. We validated these new concepts through industrial processor designs in 90-nm low-power CMOS. For standard-Vthimplementations, we observed performance-per-area improvements up to 40%, area and leakage reductions up to 30%, and dynamic power savings of up to 10% without performance penalties as a benefit from our proposed body-bias-driven design strategy. The benefits are larger for high-Vthimplementations. In this case, we observed performance-per-area improvements up to 90%, area and leakage reductions up to 40%, and dynamic power savings of up to 25% without performance penalties.

Sub-threshold circuit design has become a popular approach for building energy efficient digital circuits. The main drawbacks are performance degradation due to the exponentially reduced driving current, and the effect of increased sensitivity to process variation. To obtain energy savings while reducing performance degradation, we propose the design of a robust sub-threshold library and post-silicon tuning using an adaptive fuzzy logic controller which performs body bias scaling. We show that our methodology is able to fix the performance, consequently, making the system more energy efficient and achieving maximum yield.

We propose a new fully-integrated forward body bias (FBB) generator that holds its voltage constant relative to the (scalable) power supply of a digital IP. The generator is modular and can drive distinct digital IP block sizes in multiples of up to 1mm2. The design has been implemented in 90nm low-power CMOS. Our basic unit for driving digital IP blocks up to 1mm2occupies a silicon area of 0.03mm2only. The generator completes a 500mV FBB voltage step within 4μs. The bandwidth of the design is 570kHz. The active current of the FBB generator alone is about 177μA for a nominal process, 1.2V supply and 85°C. The standby current is as low as 72nA at 27°C.

A new approach for structural, fault-oriented analog test generation methodology to test for the presence of manufacturing-related defects is proposed. The output of the test generator consists of optimized test stimuli, fault coverage and sampling instants that are sufficient to detect the failure modes in the circuit under test. The tests are generated and evaluated on a multistep ADC taking into account the potential fault masking effects of process spread on the faulty circuit responses. Similarly, the test generator results offer indication for the circuit partitioning within the framework of circuit performance, area and testability.

The increasingly popular sub-threshold design is strongly calling for EDA support to estimate noise margins, minimum functional supply voltage, as well as the functional yield. In this paper, we propose a fast, accurate and statistical approach to accomplish these goals. First, we derive close-form functions based on a new equivalent resistance model which enables the fast estimation of noise margins of individual cells at the gate-level. Second, we propose to calculate and propagate the noise margin information with an affine arithmetic model that takes into account process variations and correspondent inter-cell correlations. Experiments with ISCAS benchmarks have shown that the new approach has an accuracy of 98.5% w.r.t. transistor-level Monte Carlo simulations. The running time per input vector of the new approach only needs a few seconds, in contrast to the many hours required by transistor-level DC Monte-Carlo simulations. To the best of our knowledge, we are the first to provide a fast, accurate and statistical methodology other than Monte-Carlo simulation for the noise margin estimation of sub-threshold combinational circuits.

A new approach for diagnostic analysis of static errors in multi-step ADC based on the steepest-descent method is proposed. To set initial data, estimate the parameter update and to guide the test, dedicated sensors have been designed. The information obtained through monitoring process variations is re-used and supplement the circuit calibration. The technique also allows the test procedure to test only for the most likely group of faults induced by a manufacturing process. The implemented design-for-test approach permits circuit reconfiguration in such a way that all sub-blocks are tested for their full input range allowing full observability and controllability of the device under test.

Operating digital circuits in the sub-threshold region is potentially a solution for ultra low-power applications. However, simply reducing supply voltage well below threshold voltage causes functional yield degradation. In this paper, we show that imbalanced VT of pMOS and nMOS transistors and VT mismatch of paired transistors are especially detrimental to sub-threshold functional yield. We propose a variability-driven digital gate design approach which includes balancing process-corner VT shifts of nMOS/pMOS transistors with a low-overhead bulk-bias circuitry and a gate-sizing approach that yields close to minimum size transistor dimensions. Results of Monte-Carlo simulations of a ring oscillator with 31 stages show that our solution can help to achieve a mean frequency speedup of 51.91% and energy/cycle saving of 19.67% on average.

The use of power switches in modern system chips (SOCs) is inevitable as they allow for efficient on-chip static power management. Leakage is today one of the main hurdles in low-power applications. Power switches enable power gating functionality, i.e., one or more parts of the SOC can be powered-off during standby mode leading in this way to savings in the overall SOCs power consumption. In this paper, we present a circuit and a method to test power switches. The proposed method allows testing of on/off functionality. In case of segmented power switches individual failing segments can be identified as well by using the proposed test strategy. The method requires only a small number of test patterns that are easy to generate. Furthermore, the proposed method is very scalable with the number of power switches and has a very small area-overhead.

Due to its low cost, low test time and reduced test complexity, structural testing is preferred to functional whenever possible. The study presented in this paper indicates that the two low-frequency structural test methods considered, power supply current monitoring and the power supply ramping technique, provide a valuable supplement/alternative when one of the functional tests (gain, noise figure and total harmonic distortion) in the test set can be complemented or substituted by structural test and add to or maintain no loss of fault coverage.

We present an on-chip, fully-digital, power-supply control system. The scheme consists of two independent control loops that regulate power supply variations due to semiconductor process spread, temperature, and chip's workload. Smart power-switches working as linear voltage regulators are used to adjust the local power supply. The smart power-switch allows us to keep the global power network unchanged. It offers an integrated standby mode and has a fast dynamic response, i.e. low transition times between voltage steps at the cost of the reduced power conversion efficiency when compared to complex DC-DC converters

Stability testing of SRAMs has been time consuming. This paper presents a new programmable DFT technique for detection of stability and data retention faults in SRAM cells. The proposed technique offers extended flexibility in setting the weak overwrite test stress, which allows to track process changes without time-consuming post-silicon design iterations. Moreover, it does not introduce extra circuitry in the SRAM array and surpasses the data retention test in test time and detection capability

In this paper we present a comparison of the results obtained between functional testing and applying the multi-VDD approach on an RF circuit. The multi-VDD approach incorporates both VDD ramp and DC ramp techniques. The VDD ramp technique has been previously evaluated on standalone devices with good results as presented in J. Pineda de Gyvez et al. (2004) and S. Ozev and A Orailoglu (2001). However, most of the work has been accomplished in the Lab. Here we present results obtained by applying the concepts in a production environment. Correlations between the functional and the multi-VDD methodologies are shown. The studies are conducted using a WLAN 802.11a transceiver.

This paper reports a design for testability technique, which provides necessary diagnostic capability for signature-based testing of analog circuits. To facilitate this kind of testing, it is preferable to observe the current (or voltage) signatures of individual cores instead of observing the current (or voltage) signature of the whole analog SoC. Therefore, our DfT works like a power-scan chain aimed at turning on/off analog cores in an individual manner, providing an observability means at the core's power and output terminals, and at exciting the core under test. The proposed DfT can be used for engineering pre-characterization as well, and can easily be interfaced to standards like I2C and IEEE 1149.1 TAP controllers. In this paper, we further provide experimental evidence of our approach as applied to an RF device

We propose a monitor able to detect on-line excessive power supply noise (PSN) at the power/ground lines. It has high resolution (100 ps), enough to collect the important features of PSN and its output is isolated from the local PSN. It is useful for any scheme that takes corrective actions to prevent signal integrity faults after detection of excessive PSN.

FPGAs are not energy efficient largely due to their programmable, capacitively loaded interconnect. We propose a new low energy FPGA interconnect architecture that is based on low energy switch blocks using Dynamic Threshold CMOS (DTMOS) based switches and an encoded-low swing (EL) technique. The presented case study, based on circuit simulations using SPICE in CMOS 0.13 micron process technology, illustrates that a 41% energy reduction can be achieved compared to the conventional techniques. A one to one comparison between NMOS based switches and the proposed DTMOS based switches reveal that the latter have a 36% lower power-delay product. We also show through a model analysis and circuit simulations that using low swing on interconnect, a timing budget can be met at 30% less energy consumption.

We propose a new low energy FPGA interconnect fabric that is based on low energy switch blocks using Dynamic Threshold CMOS (DTMOS) based switches and an encoded-low swing (EL) technique. The presented case study illustrates that the encoded-low swing technique and Dual Threshold MOS based switches results in 41% energy reduction compared to the conventional technique using full swing signalling and NMOS pass transistor based switches. We also show through a theoretical analysis, that a certain timing budget can be met by the EL technique, using 11% more buffered switches, but still consuming 62% less energy than conventional techniques. Circuit simulations, taking also the transmitter and receiver complexity into account, are in line with the model results and indicate that a timing budget can be met at 30% less energy consumption. All our results are based on CMOS 0.13μ process technology and are done using a transistor level simulator.

In this paper we examine the expectations and limitations of design technologies such as adaptive voltage scaling (AVS) and adaptive body biasing (ABB) in a modern deep sub-micron process. To serve this purpose, a set of ring oscillators was fabricated in a 90nm triple-well CMOS technology. The analysis hereby presented is based on two ring oscillators running at 822MHz and 93MHz, respectively. Measurement results indicate that it is possible to reach 13.8x power savings by 3.4x frequency downscaling using AVS, ±11% power and ±8% frequency tuning at nominal conditions using ABB only, 22x power savings with 5x frequency downscaling by combining AVS and ABB, as well as 22x leakage reduction.

An innovative approach for testing PLLs in open loop-mode is presented. The operational method consists of ramping the PLL's power supply by means of a periodic sawtooth signal. The reference and feedback inputs of the PLL in open-loop mode are connected to the clock reference signal or to ground. Then, the corresponding quiescent current, clock output, and oscillator control voltage signatures are monitored and sampled at specific times. When the power supply is swept, all transistors are forced into various regions of operation causing the sensitivity of the faults to the specific stimulus to be magnified. The developed method of structural testing for PLLs yields high fault coverage results making it a potential and attractive technique for production wafer testing.

SRAM cell stability has become an important design and test issue owing to significant process spreads, non-ideal operational conditions, and subtle manufacturing defects in scaled-down geometries. In this article, we carry out an extensive SRAM SNM sensitivity analysis and propose an SRAM cell stability fault model for weak cell detection. This fault model is used to design and verify a proposed digitally programmable design-for-test (DFT) technique targeting the weak cell detection in embedded SRAMs (eSRAM).

This paper presents the implementation of a built-in current sensor that includes two recently reported new techniques for I/sub DDQ/ testing to take into account the increased background current of defect-free circuits and its increased variance due to process variations. These techniques are the correlation between speed and I/sub DDQ,/ and the /spl Delta/I/sub DDQ/ testing technique. The monitor has been manufactured in a 0.18 /spl mu/m CMOS technology and it is based on the principle of disconnecting the device under test from the power supply during the testing phase. The monitor has a resolution of 1 /spl mu/A for a background current less than 100 /spl mu/A or 1% of background currents over 100 /spl mu/A to a total of 1 mA fullscale. The sensor operates at a maximum clock speed of 250 MHz. The monitor has been verified in a test chip consisting of one "DSP like" circuit of about 250,000 transistors. Experimental results prove the usefulness of our approach as a quick and effective means for detecting defects.

We present industrial results of a quiescent current testing technique suitable for RF testing. The operational method consists of ramping the power supply and of observing the corresponding quiescent current signatures. When the power supply is swept, all transistors are forced into various regions of operation. This has as advantage that the detection of faults is done for multiple supply voltages and corresponding quiescent currents, enhancing in this form the detectability of faults. We found that this method of structural testing yields fault coverage results comparable to functional RF tests making it a potential and attractive technique for production wafer testing due to its low cost, low testing times and low frequency requirements. 1.

A reduced intrinsic threshold voltage (V/sub T/) in addition to its variability has a direct impact on circuit design. Worst-case design styles assume that all transistors use the same worst-case V/sub T/ whose average and standard deviation come from inter-die statistical variations. However, intra-die differences, such as random local V/sub T/ variations are not considered and may pose a serious problem for designs based on low-voltage low-power premises, e.g. clock skews, excessive leakage current, out of spec critical-path delays, etc. This paper formulates a fault model based on threshold voltage mismatch and analyzes its impact on circuit design. Simulation and experimental results support the fault model.

Functional yield is a term used to describe the percentage of dies on a wafer that are not affected by catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires and cuts, which result in broken wires. Functional yield is therefore determined by the geometry of the routing channels, how these channels are filled with wire and the distribution of defect sizes. Since the wire spacing and width are usually fixed and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Previous work in this area has analyzed the problem by assuming that all wiring tracks are occupied with wire, leading to overestimates for the probability of failure due to both cuts and bridges. This paper utilizes statistical models of the placement/routing process to provide a more realistic approach for cut and bridge yield estimation. A comparison of the predicted probability of failure within each wiring layer with postlayout data indicate an average error of 20% for cuts and 26% for bridges.

In a product engineering environment there is a need to know quickly the average standby current of an IC for various combinations of power supply and temperature. We present two techniques to do this estimation without resorting to involved simulations. We use a bottom-up methodology that propagates the effect of process variations to higher levels of abstraction. In one approach, the leakage current of any given circuit is computed by adding up individual cell currents indexed from a statistically characterized library of standard cells. The second method is based on empirical formulae derived from results of the standard cell library characterization. In this approach the total leakage current is estimated without the need for any simulations and using only the circuit's equivalent cell-count. We present here the statistical foundation of our approach as well as experimental results on actual ICs.

A practical system approach for time-multiplexing cellular neural network (CNN) implementations suitable for processing large and complex images using small CNN arrays is presented. For real size applications, due to hardware limitations, it is impossible to have a one-on-one mapping between the CNN hardware cells and all the pixels in the image involved. This paper presents a practical solution by processing the input image, block by block, with the number of pixels in a block being the same as the number of CNN cells in the array. Furthermore, unlike other implementations in which the output is observed at the hard-limiting block, the very large scale integrated (VLSI) architecture hereby described monitors the outputs from the state node. While previous implementations are mostly suitable for black and white applications because of the thresholded outputs, our approach is especially suitable for applications in color (gray) image processing due to the analog nature of the state node. Experimental complementary metal-oxide-semiconductor (CMOS) chip results in good agreement with theoretical results are presented.

When low-level hardware simulations of cellular neural networks (CNNs) are very costly for exploring new applications, the use of a behavioral simulator becomes indispensable. This paper presents a software prototype capable of performing image processing applications using CNNs. The software is based on a CNN multilayer structure in which each primary color is assigned to a unique layer. This allows an added flexibility as different processing applications can be performed in parallel. To be able to handle a full range of color tones, two novel color mapping schemes were derived. In the proposed schemes the color information is obtained from the cell's state rather than from its output. This modification is necessary because for many templates CNN has only binary stable outputs from which only either a fully saturated or a black color can be obtained. Additionally, a postprocessor capable of performing pixelwise logical operations among color layers was developed to enhance the results obtained from CNN. Examples in the areas of medical image processing, image restoration, and weather forecasting are provided to demonstrate the robustness of the software and the vast potential of CNN.

An integrated system for image processing is proposed. The main elements of the system consist of a cellular neural network (CNN) software simulator, multiplexing hardware, and an interface between a PC and the hardware and software.

An efficient behavioral simulator for Cellular Neural Networks (CNN) is presented in this paper. The simulator is capable of performing Single-Layer CNN simulations for any size of input image, thus a powerful tool for researchers investigating potential applications of CNN. This paper reports an efficient algorithm exploiting the latency properties of Cellular Neural Networks along with numerical integration techniques; simulation results and comparisons are also presented.>

A novel approach to simulate Cellular Neural Networks (CNN) is presented in this paper. The approach, time-multiplexing simulation, is prompted by the need to simulate hardware models and test hardware implementations of CNN. For practical size applications, due to hardware limitations, it is impossible to have a one-on-one mapping between the CNN hardware processors and all the pixels of the image. This simulator provides a solution by processing the input image block by block, with the number of pixels in a block being the same as the number of CNN processors in the hardware. The algorithm for implementing this simulator is also presented, along with some simulation results and comparisons.>

This paper addresses the functional behavior of Cellular Neural Networks (CNN). The impact of variable convergence times on the proper operation of the network is discussed A test method is presented to determine the functionality of the network. The function fault models assume that the cells are unable to switch between limiting states. The proposed method attains 100% stuck-at fault coverage without any extra hardware for its implementation. Moreover, the required number of test vectors is constant and independent of the array size which makes it suitable for practical implementations. The paper discusses the new fault model, presents the algorithmic procedures and shows simulated testing results.>

Presents a methodology for fault diagnosis of analog circuits based on the observation of power supply currents. In the proposed technique, fault signature dictionaries are generated from the currents in the power supply bus. To obtain signatures rich in information for efficient diagnosis, the transistors in the circuit are forced to operate in all regions of operation by using a ramp signal at the supply instead of the conventional constant dc signal. The signatures are then clustered into different groups using a Kohonen neural network classifier. This technique has the potential to detect and diagnose single and multiple shorts as well as open circuits. The theoretical and experimental results of the proposed technique are verified using a CMOS Operational Transconductance Amplifier (OTA) circuit.>

While it is important to exhaustively verify IC designs for their functional performance, it is equally important to verify their robustness against spot defects, that is, to foresee what will happen to the design when it is exposed to defect conditions in a real manufacturing environment. One such verification is done by extracting the layout sites where defects can induce a functional failure of the design. Initial attempts to perform this verification task were based on a 'critical area extraction' of one layer at a time, neglecting the electrical significance of interrelationships between layers. A novel method to construct deterministically multilayer critical areas is presented. These critical areas are established on the theoretical basis of defect semantics and on the new concept of 'susceptible sites'. A system comprising several algorithms which in principle maintain simultaneously as many scan lines as the number of layers, in such a way that it is possible to keep track of the vertical and horizontal effects of defects, is developed.>

A method based on a deterministic geometrical construction of critical areas is presented for determining the sensitivity of layouts to spot defects. The models for fatal faults considered are bridges and cuts related to patterns in one layer. The approach, based on the concept of susceptible sites, has a complexity O(N log N), where N is the number of line segments. Only two scans are necessary to extract all susceptible sites, which then are used to compute the critical areas for a whole set of points in a domain of defect size.>

An interactive environment is presented for the analysis of yield information required on modern integrated circuit manufacturing lines. The system estimates wafer yields and wafer-yield variations, quantifies regional yield variations within wafers, identifies clusters in wafers and/or in lots, and is able to predict wafer yields via simple simulation tools. An analysis approach based on site yields makes the system independent of the product and of the technology. The analysis technique makes it possible to investigate the effects of both correlated and uncorrelated sources of yield loss. The statistical information obtained can be used to study changes in the technological process. Graphical displays in the form of wafer maps are used to represent the spatial distribution of dice in the wafer. Capabilities for such as radial and angular distribution analyses, among others, are provided to examine data, and hypothetical wafer maps are created to visualize and predict simulated wafer yields.>