Reconfigurable computing devices such as FPGAs offer application developers the ability to create solutions with a performance comparable to that of a hardware solution, but with the flexibility of software. Development tools that attempt to support popular software development languages such as C and Java have been developed to reduce the need for the FPGA developer to be trained in hardware design practices, however the tools have not been successful in mirroring all of the languages functionality. In particular most tools do not support programming with recursive functions. Previous research on mapping recursive functions to reconfigurable hardware has built a stack on the device which does not take full advantage of the massive amount of parallel resources on the reconfigurable device. This paper describes a method for mapping recursive functions to reconfigurable hardware without the use of a stack. It does this by unrolling the function on the device as it is executing. The results presented in this paper show that using this method can result in a significant performance increase when compared to a stack based implementation.

Classification of documents by genre is typically done either using linguistic analysis or term frequency based techniques. The former provides better classification accuracy than the latter but at the cost of two orders of magnitude more computation time. While term frequency analysis requires much less computational resources than linguistic analysis,it returns poor classification accuracy when the genres are not sufficiently distinct. A method that removes or approximates the expensive portions of linguistic analysis is presented.The accuracy and computation time of this method then compared with both linguistic analysis and term frequency analysis. The results in this paper show that this method can significantly reduce the computation of both time of linguistic analysis and term frequency analysis, while retaining an accuracy that is higher than that of term frequency analysis.

Recursive solutions are effective software techniques that are difficult to map into hardware due to their dependency on input size and data values. As a result, most high-level design tools do not allow for recursive calls. In this paper we present a technique for mapping the merge-sort algorithm, as a case study, into a reconfigurable system. Our mapping employs an on-line prediction method to reconfigure the necessary hardware only when the need arises, and to hide the reconfiguration delay. As a result, our implementation uses the smallest possible size hardware to sort an input data stream without prior knowledge of its length and eliminates the reconfiguration delay penalty. We outline a reconfigurable system with self-organizing multiple-buses as the communication subsystem. The processing elements and memory modules are connected to the multiple-buses as a linear array. We also demonstrate the effectiveness of adding simple LUTs to the multiple-buses in improving the throughput by allowing for pipelining at the word level.