Shu Yan

dblp:44/5507 · DBLP profile ↗
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11ranked-venue papers
5as first author
2since 2021 · last 2025
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 6 · 4 first-authorArtificial intelligence and machine learning · 2 · 1 since 2021Computer networks · 2Security and privacy · 1 · 1 first-author · 1 since 2021Databases, data management, data science and information retrieval · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
5 papers
Electronic design automation · 74% Integrated circuit design · 14% High-performance computing · 12%
Theoretical computer science
1 paper
Algorithms and data structures · 50% Mathematical optimization · 50%

Topics — the 11 heaviest of 11, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › parasitic extraction
capacitance extraction
0.232006
Fast 3-D Capacitance Extraction by Inexact Factorization and Reduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Sparse transformations and preconditioners for 3-D capacitance extraction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005
Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics · DAC 2004
Electronic design automation › physical design
parasitic extraction
0.232006
Fast 3-D Capacitance Extraction by Inexact Factorization and Reduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Sparse transformations and preconditioners for 3-D capacitance extraction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005
Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics · DAC 2004
Integrated circuit design
low-power circuit design
0.122007
On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise · DAC 2007
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming · DAC 2006
Electronic design automation
physical design
0.122007
On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise · DAC 2007
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming · DAC 2006
High-performance computing › numerical linear algebra
preconditioner
0.122006
Fast 3-D Capacitance Extraction by Inexact Factorization and Reduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Sparse transformations and preconditioners for 3-D capacitance extraction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005
Electronic design automation › power integrity
decoupling capacitance allocation
0.112007
On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise · DAC 2007
Electronic design automation › physical design › power delivery network design
power/ground network optimization
0.112007
On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise · DAC 2007
Electronic design automation › physical design › power delivery network design
decoupling capacitor budgeting
0.112006
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming · DAC 2006
Electronic design automation › circuit simulation
model order reduction
0.112006
Fast 3-D Capacitance Extraction by Inexact Factorization and Reduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Algorithms and data structures › numerical linear algebra
linear system solving
0.012004
Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics · DAC 2004
Mathematical optimization › numerical computation › numerical optimization › preconditioning
preconditioner design
0.012004
Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics · DAC 2004

Methods — techniques the papers use, named apart from their topics

incomplete LU factorization · 0.2fast multipole method · 0.1linear programming · 0.1decap budgeting · 0.1macromodeling · 0.1hierarchical refinement · 0.1dense-to-sparse transformation · 0.1charge-based budgeting · 0.1sparse transformation · 0.1incomplete factorization · 0.1incomplete cholesky factorization · 0.0algebraic transformation · 0.0
YearPublicationVenuePosition
2025 How Far Are We from Optimal Reasoning Efficiency?
abstract
Large Reasoning Models (LRMs) demonstrate remarkable problem-solving capabilities through extended Chain-of-Thought (CoT) reasoning but often produce excessively verbose and redundant reasoning traces. This inefficiency incurs high inference costs and limits practical deployment. While existing fine-tuning methods aim to improve reasoning efficiency, assessing their efficiency gains remains challenging due to inconsistent evaluations. In this work, we introduce the ***reasoning efficiency frontiers***, empirical upper bounds derived from fine-tuning a base LRM (DeepSeek-R1-Distill-Qwen-1.5B/7B) across diverse approaches and training configurations. Based on these frontiers, we propose the ***Reasoning Efficiency Gap (REG)***, a unified metric quantifying deviations of any fine-tuned LRMs from these frontiers. Systematic evaluation on challenging mathematical benchmarks, AMC23, AIME24, and AIME25, reveals significant gaps in current methods: they either sacrifice accuracy for short length or use excessive tokens to achieve sub-optimal accuracies despite high overall accuracy. To reduce the efficiency gap, we propose ***REO-RL***, a Reinforcement Learning algorithm that optimizes reasoning efficiency by targeting a sparse set of token budgets. Leveraging numerical integration over strategically selected budgets, REO-RL approximates the full efficiency objective with low error using a small set of token budgets. Experiments show that, compared to vanilla RL with outcome reward, REO-RL reduces the reasoning efficiency gap by 74.5\% and 64.2\% in the 1.5B and 7B settings. The 7B LRM fine-tuned with REO-RL achieves reasoning conciseness surpassing frontier LRMs like Qwen3 and Claude Sonnet 3.7. Ablation studies confirm the efficacy of our token budget strategy and highlight REO-RL’s flexibility across design choices. This work establishes a systematic framework for evaluating and optimizing reasoning efficiency in LRMs. We will release the related code, data, and models to support future research on efficient reasoning in LRMs.
Jiaxuan Gao, Shu Yan, Qixin Tan, Shusheng Xu, Zhiyu Mei, Kaifeng Lyu, Yi Wu 0013
NeurIPS2
2023 Development Situation and Suggestions of Data Elements in China
abstract
Although industry practices and policies related to the growth of the data factor market have been enhanced, there still remain challenges that need to be overcome, such as poor data quality, low data application, lack of basic systems (e.g. data property rights and transactions), and inadequate implementation of data security governance. Addressing these challenges requires efforts from both institutional construction and technological innovation. In addition, as the exploration of data elements continues to deepen, it is necessary to closely pay attention to the adaptability between data element systems and data technology innovation, adhere to the agile, iterative approach to continuously adjust and optimize, and maintain the balance between efficiency and fairness as well as between development and security.
Shu Yan, Sirui Zhang, Ailin Lv
TrustCom1
2019 An Efficient Wideband Spectrum Sensing Algorithm for Unmanned Aerial Vehicle Communication Networks
abstract
With increasingly smaller size, more powerful sensing capabilities and higher level of autonomy, multiple unmanned aerial vehicles (UAVs) can form UAV networks to collaboratively complete missions more reliably, efficiently, and economically. While UAV networks are promising for many applications, there are many outstanding issues to be resolved before large scale UAV networks are practically used. In this paper we study the application of cognitive radio (CR) technology for UAV communication networks, to provide high capacity and reliable communication with opportunistic and timely spectrum access. Compressive sensing is applied in the CR to boost the performance of spectrum sensing. However, the performance of existing compressive spectrum sensing schemes is constrained with nonstrictly sparse spectrum. In addition, the reconstruction process applied in existing schemes has unnecessarily high computational complexity and low energy efficiency. We proposed a new compressive signal processing algorithm, called iterative compressive filtering, to improve the UAV network communication performance. The key idea is using orthogonal projection as a bandstop filter in compressive domain. The components of primary users in the recognized subchannels are adaptively eliminated in compressive domain, which can directly update the measurement for further detection of other active users. Experiment results showed increased efficiency of the proposed algorithm over existing compressive spectrum sensing algorithms. The proposed algorithm achieved higher detection probability in identifying the occupied subchannels under the condition of nonstrictly sparse spectrum with large computational complexity reduction, which can provide strong support of reliable and timely communication for UAV networks.
Wenbo Xu 0005, Shu Yan, Jianhua He 0001
IEEE Internet Things J.3
2018 Missed Calls Encoding Technology for GPS Data Asset Circulation
Miaoqiong Wang, Pengwei Ma, Chunyu Jiang, Shu Yan
DATA6
2012 A novel range-free localization based on regulated neighborhood distance for wireless ad hoc and sensor networks
Bang Wang 0001, Yan Dong 0001, Shu Yan
Comput. Networks5
2007 On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise
abstract
Decap allocation are the primary methods for addressing the dynamic voltage noise problem of on-chip power networks. When space in the immediate proximity of a hot spot is constrained, simply adding decoupling capacitance without improving the local wiring is ineffective. Based on this key observation we proposed an effecient co-optimization of decap allocation and local wiring enhancement. The method solves a linear program (LP) iteratively and is based on the decap budgeting algorithm [10]. Experimental results on two actual chip designs demonstrate the area and run-time efficiency of the co-optimization algorithm. Moreover, it provides excellent solutions even in cases where decap allocation alone fails to provide a feasible solution.
Min Zhao 0001, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan
DAC8
2006 A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming
abstract
We propose a novel and efficient charge-based decoupling capacitance budgeting algorithm. Our method uses the macromodeling technique and effective radius of decoupling capacitance to reduce the size of the problem. We formulate the nonlinear optimization into a linear program (LP) by integrating the nodal equations across a time period of interest and through certain approximations. To reduce the error caused by linearization, we do multiple iterations of the linear program. Experimental results demonstrate that, with the proposed algorithm, even very large power networks (eg. 5 million nodes) can be optimized in a couple of hours with 1-2 transient analyses. Comparison of our algorithm with another heuristic method shows area efficiency and run time advantage of our method.
Min Zhao 0001, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu
DAC4
2006 Fast 3-D Capacitance Extraction by Inexact Factorization and Reduction
abstract
Capacitance-extraction algorithms based on the boundary element method (BEM) have to solve large linear systems. The number of unknowns equals the number of discretization panels n, which is much greater than the number of conductors m. The authors present a capacitance-extraction algorithm RedCap that first reduces the BEM system of size n into a small system of size O(m) and then solves the small system to compute the capacitances. RedCap uses a number of techniques, including the hierarchical-refinement technique of HiCap [Shi, 2002], the dense-to-sparse transformation of PHiCap [Yan, 2005], a reordering of the sparse linear system, and an incomplete LU factorization, to obtain the reduced system. RedCap achieves a significant speed improvement over previous methods. On benchmark problems with conductors in uniform and multilayer dielectrics, RedCap is up to 100 times faster than FastCap [Nabors and White, 1991] and up to four times faster than PHiCap [Yan, 2005], while restricting error to within 2% of FastCap
Shu Yan, Vivek Sarin, Weiping Shi
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2005 Sparse transformations and preconditioners for 3-D capacitance extraction
abstract
Three-dimensional (3-D) capacitance-extraction algorithms are important due to their high accuracy. However, the current 3-D algorithms are slow and thus their application is limited. In this paper, we present a novel method to significantly speed up capacitance-extraction algorithms based on boundary element methods (BEMs), under uniform and multiple dielectrics. The n/spl times/n coefficient matrix in the BEM is dense, even when approximated with the fast multipole method or hierarchical-refinement method, where n is the number of panels needed to discretize the conductor surfaces and dielectric interfaces. As a result, effective preconditioners are hard to obtain and iterative solvers converge slowly. In this paper, we introduce a linear transformation to convert the n/spl times/n dense coefficient matrix into a sparse matrix with O(n) nonzero entries, and then use incomplete factorization to produce a very effective preconditioner. For the k/spl times/k bus-crossing benchmark, our method requires at most four iterations, whereas previous best methods such as FastCap and HiCap require 10-20 iterations. As a result, our algorithm is up to 70 times faster than FastCap and up to 2 times faster than HiCap on these benchmarks. Additional experiments illustrate that our method consistently outperforms previous best methods by a large magnitude on complex industrial problems with multiple dielectrics.
Shu Yan, Vivek Sarin, Weiping Shi
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2004 Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics
abstract
Capacitance extraction is an important problem that has been extensively studied. This paper presents a significant improvement for the fast multipole accelerated boundary element method. We first introduce an algebraic transformation to convert the n x n dense capacitance coefficient matrix into a sparse matrix with O(n) nonzero entries. We then use incomplete Cholesky factorization or incomplete LU factorization to produce an effective preconditioner for the sparse linear system. Simulation results show that our algorithm drastically reduces the number of iterations needed to solve the linear system associated with the boundary element method. For the k x k bus crossing benchmark, our algorithm uses 3-4 iterations, compared to 10-20 iterations used by the previous algorithms such as FastCap [1] and HiCap [2]. As a result, our algorithm is 2-20 times faster than those algorithms. Our algorithm is also superior to the multi-scale method [3] because our preconditioner reduces the number of iterations further and applies to multiple dielectrics.
Shu Yan, Vivek Sarin, Weiping Shi
DAC1
2003 Improving boundary element methods for parasitic extraction
abstract
We improve the accuracy and speed of boundary element method (BEM) or multipole accelerated BEM for interconnect parasitic extraction. Three techniques are presented and applied to capacitance extraction: selective coefficient enhancement, variable order multipole and multigrid. Experimental results show that the techniques are effective for extracting parasitics between all pairs of conductors, or between selected pairs of conductors.
Shu Yan, Jianguo Liu 0001, Weiping Shi
ASP-DAC1