A reconfigurable wrapper provides the flexibility for a core test to utilize different bandwidths of test access mechanism (TAM) at different test time points. By using reconfigurable wrappers, the lower bound of total test application time can be achieved. However, since reconfigurable wrappers attempt to utilize TAM bandwidth as fully as possible, they often consume a lot of routing resources. In advanced technology nodes, routability has become a critical and difficult issue. In this paper, based on reconfigurable wrappers, we present the first work that studies the correlation between grid-based TAM wire routing and test scheduling. Our objective is to derive a feasible grid-based TAM wire routing solution with the minimum total test application time. Compared with previous works, the main advantage of our approach is that it can resolve the grid-based TAM wire routing congestion problem during test scheduling. Benchmark data show that our approach can effectively and efficiently minimize the total test application time under grid-based routing congestion constraints.

Although intentional clock skew can be utilized to reduce the clock period, its application in gated clock designs has not been well studied. A gated clock design includes both data paths and clock control paths, but conventional clock skew scheduling only focus on data paths. Based on that observation, in this paper, we propose an approach to perform the co-synthesis of data paths and clock control paths in a nonzero skew gated clock design. Our objective is to minimize the required inserted delay for working with the lower bound of the clock period (under clocking constraints of both data paths and clock control paths). Different from previous works, our approach can guarantee no clocking constraint violation in the presence of clock gating. Experimental results show our approach can effectively enhance the circuit speed with almost no penalty on the power consumption.

Although clock skew can be utilized to reduce the clock period, the utilization of clock skew also limits the sharing of resources (including registers and functional units). Previous works have considered the influence of clock arrival times on register sharing, but they do not pay any attention to the influence of clock arrival times on functional unit sharing. As a result, extra functional units are often required during functional unit binding. Based on that observation, in this paper, we perform the simultaneous application of register binding and functional unit binding for the high-level synthesis of nonzero clock skew circuits. Our objective is to minimize the circuit area for working with the lower bound of the clock period. Compared with previous works, benchmark data show that our approach can achieve the lower bound of the clock period with a smaller area overhead.

With the advent of deep sub micron era, design closure is becoming harder to achieve. In high-level synthesis, slack is a very effective means of tolerating uncertainties. Thus, several research efforts have been paid to study the slack-driven high-level synthesis problem. However, previous works cannot actually maximize the total slack value, because they are limited to either the operation scheduling stage or the resource binding stage. In this paper, we study the simultaneous operation scheduling and resource binding for the maximization of the total slack value. An integer linear programming approach is proposed for formally draw up the slack-driven high-level synthesis problem. Note that our approach guarantees maximizing the total slack value. Compared with the combination of previous works (i.e., slack-driven operation scheduling followed by slack-driven resource binding), experimental data show that our approach can greatly reduce the total slack value without any design overhead.

The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock period) limits the smallest standby leakage current its power gating can achieve. In this paper, we point out: in the high-level synthesis of a non-zero clock skew circuit, the resource binding (including functional units and registers) has a large impact on the maximum allowable delays of functional units; as a result, different resource binding solutions have different standby leakage currents. Based on that observation, we present the first work to draw up the timing driven power gating in high-level synthesis. Given a target clock period and design constraints, our goal is to derive the minimum-standby-leakage-current resource binding solution. Benchmark data show: compared with the existing design flow, our approach can greatly reduce the standby leakage current without any overhead.

Power gating is the most effective technique to reduce the leakage power of an idle functional unit. However, when the functional unit is turned on, a sudden discharge, called surge current, is induced. If too many functional units are turned on simultaneously, the instantaneous accumulated surge current may lead to the malfunction of the circuit. In this paper, we point out the high-level synthesis (including operation scheduling and functional unit binding) has a great impact on the maximum surge current. Then, based on that observation, we propose an integer linear program (ILP) to formally draw up the surge current minimization problem in the high-level synthesis stage. Compared with the existing design flow, benchmark data show that our approach can significantly reduce the maximum surge current without any design overhead.

This paper points out that register binding in the high-level synthesis stage has a significant impact on the clocking constraints between registers. As a result, different register binding solutions often lead to different smallest feasible clock periods. Based on that observation, we formally draw up the problem of register binding for clock-period minimization. Compared with the left edge algorithm, experimental data show that, in most benchmark circuits, our approach can greatly reduce the clock period without any overhead on the number of registers.

The combination of clock skew scheduling and delay insertion may lead to further clock period reduction. Although some previous works can minimize the clock period, they only heuristically reduce the required inserted delay. However, since the delay insertion is an ECO (engineering change order) process, minimizing the required inserted delay is very important for the design closure, In this paper, we present a linear program to formally formulate the simultaneous application of clock skew scheduling and delay insertion. Our objective is not only to achieve the lower bound of the clock period, but also to achieve the lower bound of required inserted delay. Compared with previous works, our paper has the following two significant contributions: (1) our approach is the first work that guarantees solving this problem optimally; and (2) our paper is the first proof of showing that the time complexity of this problem is polynomial.

In modern high-speed circuit design, the clock skew has been widely utilized as a manageable resource to improve the circuit performance. However, in high-level synthesis stage, the circuit is never optimized for the utilization of clock skew. This paper is the first attempt to the high-level synthesis of non-zero clock skew circuits. First, we show that the register binding in high-level synthesis stage has a significant impact on the clocking constraints between registers. As a result, different register binding solutions lead to different smallest feasible clock periods. Then, based on that observation, we formulate the problem of register binding for clock period minimization. Given a constraint on the number of registers, our objective is to find a minimum-period register binding solution. Experimental data show that, in most benchmark circuits, the lower bound of the clock period can be achieved without any extra overhead on the number of registers.