The stability and accuracy properties of exponentially fit integration algorithms applied to the test problem x=-Ax are compared with the more standard backward-Euler and semi-implicit methods. For the analysis, A in IR/sup n*n/ is assumed to be connectedly diagonally dominant with positive diagonals, as this models the equations resulting from the way MOS transistors and interconnect parasitics are treated in circuit-level timing simulation programs. Examples are used to demonstrate that all the exponential-fitting methods, and the semi-implicit methods, are much less accurate than backward-Euler for tightly coupled stiff problems, and an example is given which destabilizes one of the exponential-fitting methods. It is then proved that in the limit of large time steps, the more stable exponential-fitting methods become equivalent to a semi-implicit algorithm. It is shown that the backward-Euler, semi-implicit, and certain exponentially fit algorithms are multirate A-stable.>

The authors introduce a novel circuit model that accurately represents the temporal behavior of combinational circuits. This circuit model is the basis for the derivation of a new sensitizing criterion which provides the necessary conditions for accurate timing analysis. The authors describe the FPD timing analysis environment supported by the sensitizing criterion and present examples of its application.>

The use of simulation tools to verify the behavior of integrated circuits is a well established technique for circuit design. This paper describes a novel approach for circuit simulation that promises a significant improvement over conventional methods. The algorithm involves an explicit event driven technique that seems stable even when the accuracy of the solution is relaxed, and is able to perform automatic and dynamic partitioning of the network, thus allowing the full exploitation of latency in large digital networks. Although the basic method could be generalized for any type of circuit, in this paper the scope is limited to MOS integrated circuits.

Random variations inherent in any fabrication process may result in very low production yield. This is especially true in the fabrication of integrated circuits. Several methods have been proposed to help the circuit designer minimize the influence of these random variations. Most of these methods are deterministic and try to maximize yield by centering the nominal value of the designable parameters in the so-called region of acceptability. However, these design centering techniques require an assumption of convexity which is not valid in many real design situations. To overcome this problem a new convergent method is proposed which is based on the sequential solution of subproblems for which the convexity assumption is valid. A practical implementation of the algorithm is shown by examples to be computationally efficient.