Data dependency constraints constitute a lower bound P on the minimal clock period of single-phase clocked sequential circuits. In contrast to methods based on basic retiming, clocked sequential circuits with clock period P can always be obtained using software pipelining techniques. Such circuits can be derived by any method that can be framed in the following four-step process: Step 1, determine P; Step 2, compute a valid periodic schedule of the computational elements; Step 3, place registers back to the circuit; Step 4, assign the clock signals to control registers.Methods with polynomial run-time to implement this process are proposed in the literature. They implement these steps sequentially, starting with Step 1. These methods do not know how to optimally place registers which leads to an unnecessary number of registers. In this article, we address the problem of how to simultaneously implement Steps 2 and 3 in order to minimize the total number of registers. We conjecture that the problem is NP-hard in its general form. We formulate the problem for the first time in the literature, and devise a Mixed Integer Linear Program (MILP) to solve it. From this MILP, we derive a linear program to determine approximate solutions to the problem for large general circuits. We show that the proposed approach can handle nonzero clock skew. Experimental results confirm the effectiveness of the approach and show that significant reductions of the number of registers can be obtained although register sharing is not used. When the schedule is given, the proposed approach provides solutions to the problem of how to place the minimal number of registers in Step 3.

We address the problem of minimizing dynamic power consumption for single-phase synchronous digital designs, under timing constraints, using an unification of basic retiming and supply voltage scaling. We assume that the number of supply voltages and their values are known for each computation element. Our main objective is then to change the location of registers using basic retiming while maximizing the number of computation elements off critical paths that can operate under a low available supply voltage, and can lead to a maximum dynamic power saving. We address the problem at the system-level. We formulate the problem as a Mixed Integer Linear Program (MILP). The exact optimal solution for the problem is then guaranteed. We also devise an algorithm to compute bounds on the values assigned by basic retiming to each computational element. Besides helping to find the optimal solution to the problem, these bounds also allow to reduce the run-time for finding this solution. The proposed approach can produce converter-free designs and can also minimize short-circuit power consumption. Experimental results have shown that dynamic power consumption can be reduced by factors that range from 2.78% to 37.24% for single-phase designs with minimal clock period. For these experimental results, the run-time for solving the MILP is under 2min.

Dynamic traffic management methods constitute the intelligent core of Intelligent Transportation Systems (ITS). In order for these methods to be effective and deployable in real-time, there is a need to develop models that predict future traffic conditions in a computational time much less than real time. In this paper we report on parallel implementations for a class of Dynamic Traffic Assignment (DTA) models, known as macroscopic DTA models. This class of models possess mathematical formulations which are solved using various algorithms. Two parallel decomposition strategies based on network topology and time are investigated and implemented in a distributed memory environment. Numerical results show that for the network topology based decomposition strategy, a speed-up of 5 is observed when the number of processors is 10 and the asymptotic speed-up is about 10. For the time-based decomposition strategy a speed-up of 6.5 is observed when the number of processors is 10 and the asymptotic speed-up is about 25.

This paper presents a decentralized algorithm that can function as a component of a hybrid centralized/decentralized route guidance system. The focus of the algorithm's design is on vehicle-level communication and computation for the purpose of developing vehicle-centric route guidance. The algorithm has been implemented and tested on a sample network in which both guided and unguided vehicles are modeled. Results are given which show that the algorithm is successful at responding to small amounts of network stochasticity as well as to congestion caused by incidents.

We address the problem of minimizing dynamic power consumption under performance constraints by scaling down the supply voltage of computational elements off critical paths. We assume that the number of possible supply voltages and their values are known for each computational element. We focus on solving this problem on cyclic and acyclic graphs corresponding to synchronous designs. We consider multiphase clocked sequential circuits derived using software pipelining techniques. In this paper, we present exact and heuristic methods to solve the problem. The proposed methods take the form of mathematical programming formulations and their associated solution algorithms. The exact methods are based on a mixed integer linear programming formulation of the problem. The heuristic methods are based on linear programming formulations derived from the exact problem formulation. Solution methods are analyzed experimentally in terms of their run time and effectiveness in finding designs with lower dynamic power using circuits from the ISCAS89 benchmark suite. Power reduction factors as high as 69.75% were obtained compared to designs using the highest supply voltages. One of the heuristic methods leads to solutions that are near optimal, typically within 5% from the optimal solution. Low dynamic-power designs with no or a small number of level converters, are also obtained.

This paper extends the A* methodology to shortest path problems in dynamic networks, in which arc travel times are time dependent. We present efficient adaptations of the A* algorithm for computing fastest (minimum travel time) paths from one origin node to one destination node, for one as well as multiple departure times at the origin node, in a class of dynamic networks the link travel times of which satisfy the first-in-first-out property. We summarize useful properties of dynamic networks and develop improved lower bounds on minimum travel times. These lower bounds are exploited in designing efficient adaptations of the A* algorithm to solve instances of the one-to-one dynamic fastest path problem. The developed algorithms are implemented and their computational performance is analyzed experimentally. The performance of the computer implementations of the adaptations of the A* algorithm are compared to a dynamic adaptation of Dijkstra's algorithm, stopped when the destination node is selected. Comparative computational results obtained demonstrate that the algorithms of this paper are efficient. Using a network containing 3000 nodes, 10 000 links, and 100 time intervals, the dynamic adaptations of the A* led to a savings ratio of 11, in terms of number of nodes selected, and to a savings ratio of five in terms of computation time. The effect of the network size on the performance of these adaptations is also studied. It is shown that the computational savings in term of both the number of nodes selected and the computation time, increase with the size of the network topology.