Epileptic seizure prediction could help patients stay safe and provide them with opportunities to prevent seizures in advance. This can be realised by a complete system that captures the intracortical neuronal signals from the implantable device, processes the recorded data for discriminating seizures and transfers the information to the personal advisory device. Seizures can be discriminated by monitoring the counts of population spikes and we proposed a spike detection front-end for this application. The proposed discrete-time system amplifies, detects and digitises the spiking with ultra-low power and high precision with the aid of memristor as a trimming device. In this paper, we utilised the measurement methodology for the discrete-time system that combines periodic steady-state analysis and transient simulation to examine its behaviour under sources of uncertainty: noise, process corner and mismatch. The noise performance can be improved by oversampling while maintaining low power consumption. And the memristive devices are capable of compensating the inherent offset and do not induce material impact. Combining work and verification above, the system can be scaled up and/or practical implementation in the next step.

One of the challenges of designing neural front-end is to reject the DC offset from electrodes. The conventional AC-coupled solution is to utilise large input capacitors and pseudo-resistors, which have the key limitations of area, linearity and DC drift. In this paper, we propose a DC-coupled solution based on the hybrid CMOS/memristor technique. The spike detection is realised by thresholding in the proposed front-end, which consists of a memristive amplifier and a DLC. The amplifier boosts micro-volt neural signals to milli-volt through integration, making it recognised by the DLC. In addition, the memristor is utilised as a trimming device along the current branch for the purpose of tuning the offset voltage. It is capable of compensating up to 50mV DC offset. With the oversampling ratio reaching 95, the accuracy spike detection can be maintained to 95% and the frontend consumes 123.5nW in our design example. The proposed DC offset front-end is capable of reaching high accuracy and low power consumption.

Detecting neuronal activity for rehabilitation/assistive devices is an example of extreme edge computing, featuring stringent requirements for data bandwidth from implantable acquisition system, low-power consumption and ideally also low latency. Recently, we proposed a neural recording system which detects neural spikes directly on the signals collected from electrophysiological probes. The system achieves power efficiency by utilising a combination of integrative sensing and ultra-fine offset compensation. A central component of this design is a memristive load, which is utilised as a trimming device along the differential branches of the core amplifier, ultimately allowing system offset tuning with μν precision. Previous work has assumed that the memristive device features a linear, or nearly-linear current-voltage (IV) characteristic. In this paper, we study the impact of memristor IV non-linearity on the effective gain and offset compensation capability of the system. Results show that the non-linearity experimentally measured from our in-house metal-oxide memristor technology only induces a small gap between nominal resistive state and static RS (as reflected on the IV). This leads to a very small degradation of gain (≈ 2.5%) and offset compensation (≈ 50% increased offset tuning sensitivity), but very crucially proves that introducing IV non-linearity does not materially change either the extreme offset trimming precision or the overall performance. This was the last conceptual bottleneck identified before practical implementation and it has now been overcome.

Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.

The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems.