Increasing complexity of integrated circuits has forced the industry to abandon partial scan, which necessitates a computationally demanding and unaffordable sequential ATPG, and to rather adopt full scan despite its costs. In this paper, we propose a partial scan scheme driven by a computationally efficient test cube analysis. We tackle the challenges associated with the identification of the conditions to restore the controllability and observability compromised due to partial scan, and with the formulation of these conditions in terms of test cube operations. Upon the identification of a maximal-sized set of scan flip-flops that are converted to non-scan, a simple post-processing of the test cubes helps compute the values to be loaded into the scan flip-flops, eliminating the need to re-run ATPG while at the same time ensuring the quality of full scan. The proposed scheme combines the simplicity of the conventional ATPG flow with the area, performance, test time, and test power reduction benefits of partial scan. The proposed test cube analysis driven partial scan scheme is orthogonal and thus fully compatible with other test cost reduction techniques, such as test data compression and test power reduction, which can be applied in conjunction.

While scan-based compression is widely utilized in order to alleviate the test time and data volume problems, the overall compression level is dictated not only by the chain to channel ratio but also the ratio of encodable patterns. Aggressively increasing the number of scan chains in an effort to raise the compression levels may reduce the ratio of encodable patterns, degrading the overall compression level. In this paper, we present various methods to improve the ratio of encodable patterns. These methods are based on manipulating the care bit distribution of an unencodable pattern, thereby rendering it compliant with the correlation induced by the decompressor, and thus converting it into an encodable pattern. The proposed methods target improvements over fan-out and XOR decompressors, while they can be utilized to enhance other types of decompressors, such as multiplexer-based ones. Care bit manipulation is effected in the form of selective chain delay, selective slice rotate/invert, or both. By developing computationally efficient algorithms and cost-effective hardware blocks for these manipulation methods, we show that the encodability, and thus the compression levels, of stimulus decompressors can be significantly improved through the proposed practical and design flow compatible solution.

Scan architecture with compression support has been a de-facto solution in recent designs. It has been shown that compression levels and the quality attained highly depend on the ratio of encodable test patterns. We observe that whether a test pattern is encodable by a decompressor is a direct consequence of whether its care bit distribution is compatible with the correlation induced by the decompressor. Therefore, we present a series of “add-on” blocks that can be utilized to control the care bit distribution and thus to improve the encodability of stimulus decompressors. We show that compression levels attained by fan-out and XOR decompressors can be significantly enhanced via the proposed add-on blocks and the supporting algorithms.