Aircraft systems manage resource sharing among several uniprocessor modules operating under the ARINC 653 specification. This standard, based on a two-level hierarchical architecture, guarantees function isolation within partitions. Partitions are scheduled on the processor according to an infinitely repeated offline statically defined cycle. During each cycle, a partition may be accessed either once or multiple times. This study focuses on the case where each partition is granted a single processor access per cycle. We propose an approach that involves transforming a two-level hierarchical scheduling model into a conventional uni-level system. This transformation enables the application of existing results from non-hierarchical uniprocessor scheduling for analysis. We establish a correlation between the schedulability properties of both systems and derive an exact schedulability criterion for fully harmonic task sets. Additionally, we extend this approach to compute precise worst-case response times of tasks within a two-level hierarchical system, leveraging established uniprocessor schedulability results. Finally, we evaluate the scalability of this method.

Discussions surrounding Industry 5.0 emphasize the need for a fully interconnected industrial ecosystem, integrating AI and digital twins. In this environment, industrial equipment must collaborate seamlessly with human workers, requiring low-latency, high-data-rate connectivity for real-time monitoring. To address this demand, Time-Sensitive Networking (TSN) standards have been developed. However, configuring TSN in dynamic industrial networks poses challenges. The IEEE 802.1Q standard offers mechanisms like the Time-Aware Shaper (TAS) to achieve deterministic latency when configured correctly. In this paper, we tackle the configuration of TAS in dynamic networks, like reconfiguration of production lines to fit production objectives or the deployment of new applications in the production line resulting in adding new flows in the network. Our solution employs Deep Reinforcement Learning (DRL), trained and evaluated through simulations, offering adaptability to changing network conditions and dynamic production line reconfigurations.

Industry 4.0 involves the networking of production equipment. This can be achieved thanks to the Time-Sensitive Networking (TSN) set of network standards. However, this new paradigm brings new challenges because TSN features optimization relies on the dynamic characteristics of the underlying communication network (e.g., network topology, routing strategy, critical flows requirements, etc.). This paper focuses on the case of the IEEE 802.1Qbv standard by exploring the applicability of a Deep Reinforcement Learning (DRL) approach in order to reduce the configuration time of the TSN-specific parameters, compared to exact or heuristic methods.

We demonstrate that, for periodic systems with offsets (tasks or flows of messages within a time-triggered network), the simulation cycle can be confined to the range of [0, hyperperiod) only under the condition that an idle point exists at the hyper-period. Furthermore, we establish that ensuring both (1) contention-freedom and (2) that no offset exceeds the value of the period minus duration, is a sufficient condition to guarantee the presence of an idle point at the hyper-period. Most contemporary methods aiming to eliminate latency are implicitly based on these properties and fail to propose a schedule if the input system does not allow a contention-free solution. Consequently, we propose a heuristic approach to scheduling periodic flows of frames within time-triggered networks. Our method focuses on minimizing latency, without necessitating a solution where every frame at every output port is contention-free, and it effectively manages the cyclicity problem.

Packet switched networks and message multiplexing have been a major upgrade for industrial systems communications. In the avionics domain, this evolution was brought by the introduction of avionics full duplex switched ethernet (AFDX). Guaranteed upper bounds of end-to-end delays for messages transmitted over an AFDX network are mandatory for certification reasons. In this article, we present the forward end-to-end delay analysis (FA), which is scalable to both large and heavily loaded configurations. A formal proof of FA is detailed and the approach is compared with alternative methods (network calculus and the trajectory approach) on two types of AFDX configurations (including a real industrial architecture).

Avionics Full DupleX Switched Ethernet (AFDX) switches, used in major civilian aircraft, have flow differentiation capability via multiple levels of Fixed Priority (FP) traffic classes. Inside a class, frames are handled in a First In First Out (FIFO) manner. End-to-end (ETE) delays, in such a network, have to be determined and an upper-bound is mandatory for certification purpose. Several methods, such as Network Calculus (NC) and Trajectory Approach (TA), can compute worst-case ETE delays in both FIFO and FP/FIFO contexts. The Forward end-to-end delay Analysis (FA) has been formerly developed for FIFO scheduling, and in this paper, we extend it to cover also FP/FIFO. We apply to the approach an optimization related to flow serialization, which has already proven to be effective for other methods and other servicing strategies. Finally, we apply FA on a sample configuration and compare the results to the two aforementioned approaches (TA and NC).

The AFDX (Avionics Full DupleX Switched Ethernet) is the backbone network of most modern civilian aircraft. For certification reasons, a guaranteed upper bound has to be determined on the end-to-end delay for all transmitted flows. Several approaches have been designed in order to analyze such delays. In this paper, we focus on the Forward End-to-End delays Analysis (FA). This method is based on real-time scheduling results. Our goal is to propose an improvement, that reduces the pessimism of the computed bounds, compared to earlier versions of the method. The improvement relies on the way the serialization of packets sharing a common link is taken into account. We also propose a comparative analysis on a simple configuration with two other methods (Network Calculus and the Trajectory approach).

AFDX (Avionics Full Duplex Switched Ethernet) is a network designed for safety-critical applications in avionics systems. The flow analysis is mandatory for the certification. The end-to-end (ETE) delay upper bound has to be computed and hence guaranteed. Different approaches have been proposed to compute ETE delay upper bound such as the Network Calculus and the trajectory method. Both methods are deemed to introduce some pessimism in the computations. We only focus next on the trajectory approach. This paper shows that the original trajectory approach is flawed and can compute an optimistic ETE. We present a counter-example and discuss the sources of optimism that must be considered to revise the trajectory method.

Worst case backlog evaluation is a key issue to avoid under or over sizing of output port buffers for store-and-forward switches. Typically, the dimensioning of switches in the context of avionics is at least as important as the upper bounding of the end-to-end delays. This paper presents a new method based on the Trajectory approach for backlog evaluation of output ports of AFDX switches. On an industrial AFDX configuration, this new method leads to an average buffer size reduction of 10% compared to the existing Network Calculus approach.

AFDX (Avionics Full Duplex Switched Ethernet) standardized as ARINC 664 is a major upgrade for avionics systems. But network delay analysis is required to evaluate end-to-end delay's upper bounds. The Network Calculus approach, that has been used to evaluate such end-to-end delay upper bounds for certification purposes, is shortly described. The Trajectory approach is an alternative method that can be applied to an AFDX avionics network. We show on an industrial configuration, in which cases the Trajectory approach outperforms the existing end-to-end delays upper bounds and how the combination of the two methods can lead to an improvement of the existing analysis.

Avionics Full Duplex Switched Ethernet (AFDX) standardized as ARINC 664 is a major upgrade for avionics systems. The mandatory certification implies a worst-case delay analysis of all the flows transmitted on the AFDX network. Up to now, this analysis is done thanks to a tool based on a Network Calculus approach. The more recent Trajectory approach has been proposed for the computation of worst-case response time in distributed systems. This paper shows how the worst-case delay analysis of the AFDX can be improved using an optimized Trajectory approach. The Network Calculus and the Trajectory approaches are compared on a real avionics AFDX configuration. Moreover, an evaluation of an upper bound of the pessimism of each approach is proposed.

AFDX (avionics full duplex switched Ethernet) standardized as ARINC 664 is a major upgrade for avionics systems. But network delay analysis is required to evaluate end-to-end delay's upper bounds. The network calculus approach, that has been used to evaluate such end-to-end delay upper bounds for certification purposes, is shortly described. In this paper we present how the trajectory approach can be applied to an AFDX avionics network. Moreover we explain how this approach can be optimized in this context. We show that, on an industrial configuration, it outperforms existing end-to-end delays upper bounds.