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Buddika Sumanasena

dblp:44/8859 · also M. G. Buddika Sumanasena · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2008
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 91% Processor architecture and microarchitecture · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › digital circuit design
arithmetic circuit design		 0.112008
A Scale Factor Correction Scheme for the CORDIC Algorithm · IEEE Trans. Computers 2008
Integrated circuit design › digital arithmetic circuits
CORDIC		 0.112008
A Scale Factor Correction Scheme for the CORDIC Algorithm · IEEE Trans. Computers 2008
Integrated circuit design
digital circuit design		 0.112008
A Scale Factor Correction Scheme for the CORDIC Algorithm · IEEE Trans. Computers 2008
Processor architecture and microarchitecture › computer arithmetic
fixed-point arithmetic		 0.012008
A Scale Factor Correction Scheme for the CORDIC Algorithm · IEEE Trans. Computers 2008
YearPublicationVenuePosition
2008 A Scale Factor Correction Scheme for the CORDIC Algorithm
abstract
A method for the correction of scale factor of the CORDIC algorithm is presented in this paper. The scheme requires some additional hardware for its implementation, but does not require changing the elementary rotation angles or the sequence of iterations of the standard CORDIC algorithm. Upper bounds for the quantization error when using the proposed method are derived. A word serial implementation of the algorithm is also given. For fixed point arithmetic area and latency of the proposed implementation is compared with the standard CORDIC.
Buddika Sumanasena
 IEEE Trans. Computers1