The performance advantages in parallel ring-based VCOs are explored. When the number of VCOs is doubled, the parallel VCOs enhance phase noise by 3dB, and the within-chip process-induced variation is reduced by 3dB, which improves chip-limited yield. The parallel VCOs trade off circuit area and power in exchange. The parallelism advantages in analog and digital systems are compared.

This paper presents a statistical framework to cooperatively design and develop technology, product circuit, benchmarking and model early in the development stage. The statistical data-driven approach identifies device characteristics that are most correlated with a product performance, and estimates performance yield. A statistical method that isolates systematic process variations on die-to-die and wafer-to-wafer levels is also presented. The proposed framework enables translations of interactions among technology, product, and model, and facilitates collaborative efforts accordingly.

A scalable and modular delta-sigma modulator readout architecture and an implementation for an array-based sensor system are presented. The proposed readout system has parallel finite impulse response (FIR) filters that are one-to-one mapped to a large-scale array of delta-sigma modulators. The proposed filter uses bit-serial arithmetic, and it provides simultaneous and continuous filtering and readout capability to double the effective sample rate with a single concurrent conversion and readout phase. The oversampling rate and the filter coefficients can be adjusted flexibly to the design needs, and the filter array size can be increased modularly with a minimal additional circuits. A prototype filter module with a 255-tap FIR filter shows maximum 95MSamples/sec in 0.18 mum CMOS technology, and an array of 256 filter modules produces 377kFrames/sec. A filter module is about 145 mum wide and 7.45 mum high

A mixed-signal implementation of an iterative bound-based nonlinear data acquisition decoding algorithm for first-order delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converters (ADCs) is discussed. The design is partitioned into analog and digital sections which optimize the design objectives of very small area while maintaining low power and high speed. The circuit has been realized using 0.7mm/sup 2/ in 0.5/spl mu/m CMOS technology and is estimated to occupy 0.44mm/sup 2/ without test circuits.