Multi-FPGA prototyping, because of its low cost, high speed, and real world testing is quite popular today for pre-silicon verification of increasingly complex designs. In this work, we present a novel exploration flow that is used to analyze and optimize the multi-FPGA based prototyping of complex digital designs. In this flow, an end-to-end experience starting from benchmark generation to optimized inter-FPGA routing is given. For inter-FPGA routing, timing-driven approach is used instead of previously used routability-driven approach. Ten large designs are generated using generic tools of the flow and then effect of number of FPGAs on board, number of inter-FPGA tracks is observed on the performance of generated designs. Extensive experimentation reveals that FPGA board with six FPGAs gives best system frequency results. Furthermore, execution time comparison between routability and timing-driven approach reveals that compared to routability-driven approach, timing-driven approach consumes, on average, 46% less time while giving same or better frequency results.

We introduce the class of multiply constant-weight codes to improve the reliability of certain physically unclonable function response, and extend classical coding methods to construct multiply constant-weight codes from known \(q\) -ary and constant-weight codes. We derive analogs of Johnson bounds and give constructions showing these bounds to be asymptotically tight up to a constant factor under certain conditions. We also examine the rates of multiply constant-weight codes and demonstrate that these rates are the same as those of constant-weight codes of corresponding parameters.

The function M(m, n, d, w), the largest size of an unrestricted binary code made of m by n arrays, with constant row weight w, and minimum distance d is introduced and compared to the classical functions of combinatorial coding theory Aq(n, d) and A(n, d, w). The analogues for systematic codes of A(n, d) and A(n, d, w) are introduced apparently for the first time. An application to the security of embedded systems is given: these codes happen to be efficient challenges for physically unclonable functions.

This paper presents an easy to design Physically Unclonable Function (PUF). The proposed PUF implementation is a loop composed of N identical and controllable delay chains which are serially assembled in a loop to create a single ring oscillator. The frequency discrepancies resulting from the oscillator driven by complementary combinations of the delay chains allows to characterize one device. The presented PUF, nicknamed the Loop PUF (LPUF), returns a frequency comparison of loops made of N delay chains (N ≥ 2). The comparisons are done sequentially on the same structure. Unlike others PUFs based on delays, there is no specific routing constraints. Hence the LPUF is particularly flexible and easy to design. The basic use of the Loop PUF is to generate intrinsic device keys for cryptographic algorithms. It can also be used to generate challenge response pairs for simple authentication. Experiments have been carried out on CYCLONE II FPGAs to assess the performance of the LPUF, such as randomness, uniqueness and steadiness. They clearly show both the easiness of design and the quality level of the LPUF. The measurement time vs steadiness, as well as resistance against side-channel and modeling attacks are discussed.