EDBT 2026 Demo / reviewers in the wild / expert
Shri Vishakh Devanand
dblp:440/7891
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2026
0009-0003-9171-6054ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Performance modeling and evaluation · 61% Memory systems · 30% Cloud and datacenter computing · 9% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › memory disaggregation
CXL memory |
1.0 | 1 | 2026 | CXLMemSim: Practical Performance Simulation and Characterization of CXL 3.0 Memory Systems · HPDC 2026 |
Performance modeling and evaluation › simulation › architectural simulation
memory system simulation |
1.0 | 1 | 2026 | CXLMemSim: Practical Performance Simulation and Characterization of CXL 3.0 Memory Systems · HPDC 2026 |
Performance modeling and evaluation
simulation |
1.0 | 1 | 2026 | CXLMemSim: Practical Performance Simulation and Characterization of CXL 3.0 Memory Systems · HPDC 2026 |
Methods — techniques the papers use, named apart from their topics
eBPF tracing · 1.0PEBS tracing · 1.0LBR tracing · 1.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | CXLMemSim: Practical Performance Simulation and Characterization of CXL 3.0 Memory SystemsabstractCompute Express Link (CXL) 3.0 can turn stranded DRAM into a composable datacenter memory fabric, but hardware is scarce and cycle-accurate simulation is prohibitively slow for full workloads. CXLMemSim is an open-source software CXL memory simulator that keeps computation at native speed and models only CXL-affected memory behavior. Across SPEC CPU2017, Memcached, wrf, vector search, and llama.cpp, CXLMemSim stays within 11–15% of hardware and gem5 while completing a Redis-scale run in 45 minutes instead of gem5’s 73 hours. The public release at SlugLab/CXLMemSim provides PEBS/LBR/eBPF tracing, JSON topology descriptions, and reusable migration/cache policy hooks for CXL design-space exploration. Yiwei Yang 0002, Shri Vishakh Devanand, Brian Zhao, Yusheng Zheng, Pooneh Safayenikoo, Tanvir Ahmed Khan 0001, Andi Quinn |
HPDC | 2 |