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Alexandros Moiras

dblp:441/0872 · DBLP profile ↗
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2ranked-venue papers
1as first author
2since 2021 · last 2026
0009-0001-3391-1009ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
GPUs and heterogeneous computing · 51% Processor architecture and microarchitecture · 26% Performance modeling and evaluation · 15%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
GPUs and heterogeneous computing
GPU architecture
1.012026
AccelHSA: Modeling Single-ISA Heterogeneous GPU Architectures · ACM Trans. Archit. Code Optim. 2026
GPUs and heterogeneous computing
GPU microarchitecture
1.012026
AccelHSA: Modeling Single-ISA Heterogeneous GPU Architectures · ACM Trans. Archit. Code Optim. 2026
Processor architecture and microarchitecture › multicore design › heterogeneous multicore
single-ISA heterogeneous cores
1.012026
AccelHSA: Modeling Single-ISA Heterogeneous GPU Architectures · ACM Trans. Archit. Code Optim. 2026
Performance modeling and evaluation › simulation › architectural simulation
cycle-accurate simulation
0.312026
AccelHSA: Modeling Single-ISA Heterogeneous GPU Architectures · ACM Trans. Archit. Code Optim. 2026
Performance modeling and evaluation › simulation › parallel architecture simulation
GPU simulation
0.312026
AccelHSA: Modeling Single-ISA Heterogeneous GPU Architectures · ACM Trans. Archit. Code Optim. 2026

Methods — techniques the papers use, named apart from their topics

cycle-accurate simulation · 1.0
YearPublicationVenuePosition
2026 sCROOGe: Circuit-level Design and Optimization Framework for RISC-V Out-of-Order GPUs
Maria Zerva, Panagiotis-Eleftherios Eleftherakis, Alexis Maras, Konstantinos Iliakis, Alexandros Moiras, Sotirios Xydis
ISCA5
2026 AccelHSA: Modeling Single-ISA Heterogeneous GPU Architectures
abstract
Initially branded as dedicated graphics processing accelerators, GPUs now find applications in an ever-growing range of domains, including artificial intelligence, high-performance computing, self-driving vehicles, and bioinformatics. However, this diversity comes at the cost of reduced resource efficiency and micro-architectural affinity. Evidently, the homogeneity of the GPU hardware struggles to cope with the vast heterogeneity of GPU applications. Motivated by the aforementioned observations, this article introduces the concept of Single-ISA Heterogeneous GPU architectures. In order to explore the efficiency of the new GPU architectural paradigm, we extend Accel-Sim, the state-of-the-art, cycle-accurate GPU simulator to support single-ISA heterogeneous cores within the GPU chip. The proposed implementation, called AccelHSA, supports independently tuning the micro-architectural characteristics of the cores, unlocking a wide design space. The CUDA API is extended to allow control of the kernel-to-core-type mapping along with a newly developed kernel launching model that supports concurrent execution, aimed at, albeit not limited to, the context of the simulator. We showcase the impact of single-ISA heterogeneous GPU architectures via a case study targeting the collocation of resource sensitive and insensitive HPC kernels. Finally, the heterogeneous GPU architecture is evaluated against homogeneous GPU baselines, demonstrating a 27.07% average speedup with a marginal 0.47% area overhead.
Alexandros Moiras, Konstantinos Iliakis, Dimitrios Soudris, Sotirios Xydis
ACM Trans. Archit. Code Optim.1