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Yufei Shangguan

dblp:441/1663 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2026
0009-0006-1544-2356ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Performance modeling and evaluation · 56% Hardware accelerators and domain-specific architectures · 44%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Performance modeling and evaluation
analytical modeling
1.012026
NPUMeter: Automatic Operator Optimization for Ascend NPU with Accurate Analytical Performance Models · ACM Trans. Archit. Code Optim. 2026
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
neural processing unit
1.012026
NPUMeter: Automatic Operator Optimization for Ascend NPU with Accurate Analytical Performance Models · ACM Trans. Archit. Code Optim. 2026
Performance modeling and evaluation › performance prediction
latency prediction
0.312026
NPUMeter: Automatic Operator Optimization for Ascend NPU with Accurate Analytical Performance Models · ACM Trans. Archit. Code Optim. 2026

Methods — techniques the papers use, named apart from their topics

design space exploration · 1.0analytical performance modeling · 1.0
YearPublicationVenuePosition
2026 NPUMeter: Automatic Operator Optimization for Ascend NPU with Accurate Analytical Performance Models
abstract
With the rapid development of AI and deep learning, computational demands are increasing significantly. While GPUs excel in parallel computing, they fall short in terms of energy efficiency, specialization, and processing latency. In contrast, Neural Processing Units (NPUs), such as the Ascend NPUs, designed specifically for deep learning tasks, demonstrate superior performance. However, the architecture specialization makes operator development more challenging, leading to a reliance on manual tuning and optimization, which incurs significant time cost and developing effort. To address this issue, we propose NPUMeter, an automatic operator optimization framework for Ascend NPUs built upon accurate and comprehensive analytical performance models. NPUMeter comprises two components: (1) an analytical performance model that accurately estimates operator latency on NPU given different configurations of optimization parameters; (2) an efficient design space exploration (DSE) algorithm that automatically searches for the optimal parameter configuration in a large design space within minutes. Experimental results demonstrate that NPUMeter achieves high estimation accuracy, with an average error below 5%. It effectively generates near-optimal configurations for various operators, achieving up to a 1.46× performance speedup compared to the configuration generated by the Ascend C compiler while reducing the DSE time from hours to minutes.
Weichuang Zhang, Yufei Shangguan, Yuting Mai, Qiuliang Wang, Chen Chen 0067, Quan Chen 0002, Wenchao Ding 0001, Jieru Zhao, Minyi Guo
ACM Trans. Archit. Code Optim.2