EDBT 2026 Demo / reviewers in the wild / expert
Gilbert C. Sih
dblp:45/1336
· DBLP profile ↗
3ranked-venue papers
3as first author
0since 2021 · last 1993
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Parallel and multicore computing · 44% Embedded and real-time systems · 44% Interconnection networks and networks-on-chip · 11% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Embedded and real-time systems › real-time scheduling
pre-run-time scheduling |
0.0 | 2 | 1993 | Declustering: A New Multiprocessor Scheduling Technique · IEEE Trans. Parallel Distributed Syst. 1993 A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures · IEEE Trans. Parallel Distributed Syst. 1993 |
Parallel and multicore computing
task scheduling |
0.0 | 2 | 1993 | Declustering: A New Multiprocessor Scheduling Technique · IEEE Trans. Parallel Distributed Syst. 1993 A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures · IEEE Trans. Parallel Distributed Syst. 1993 |
Parallel and multicore computing › task scheduling
communication-aware scheduling |
0.0 | 1 | 1993 | A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures · IEEE Trans. Parallel Distributed Syst. 1993 |
Parallel and multicore computing › parallel scheduling
heterogeneous multiprocessor scheduling |
0.0 | 1 | 1993 | A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures · IEEE Trans. Parallel Distributed Syst. 1993 |
Interconnection networks and networks-on-chip
interprocessor communication |
0.0 | 1 | 1993 | A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures · IEEE Trans. Parallel Distributed Syst. 1993 |
Embedded and real-time systems › real-time scheduling
multiprocessor scheduling |
0.0 | 1 | 1993 | Declustering: A New Multiprocessor Scheduling Technique · IEEE Trans. Parallel Distributed Syst. 1993 |
Embedded and real-time systems › model-based design › dataflow modeling
synchronous dataflow |
0.0 | 1 | 1993 | Declustering: A New Multiprocessor Scheduling Technique · IEEE Trans. Parallel Distributed Syst. 1993 |
Methods — techniques the papers use, named apart from their topics
list scheduling heuristic · 0.0graph analysis · 0.0dynamic level scheduling · 0.0declustering · 0.0clustering · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1993 | A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor ArchitecturesabstractThe authors present a compile-time scheduling heuristic called dynamic level scheduling, which accounts for interprocessor communication overhead when mapping precedence-constrained, communicating tasks onto heterogeneous processor architectures with limited or possibly irregular interconnection structures. This technique uses dynamically-changing priorities to match tasks with processors at each step, and schedules over both spatial and temporal dimensions to eliminate shared resource contention. This method is fast, flexible, widely targetable, and displays promising performance.> Gilbert C. Sih, Edward A. Lee |
IEEE Trans. Parallel Distributed Syst. | 1 |
| 1993 | Declustering: A New Multiprocessor Scheduling TechniqueabstractThe authors present a new compile-time scheduling heuristic called declustering, which schedules acyclic precedence graphs that fit the synchronous data flow (SDF) model onto multiprocessor architectures. This technique accounts for interprocessor communication (IPC) overheads and considers interconnection constraints in the architecture so that shared resource contention can be avoided. The algorithm initially invokes a new clustering method that uses graph-analysis techniques to isolate parallelism instances. When constructing an initial set of clusters, this procedure explicitly addresses the tradeoff between exploiting parallelism and incurring communication cost. By hierarchically combining these clusters and then systematically decomposing this hierarchy, the declustering method exposes parallelism instances in order of importance and attains a cluster granularity that fits the characteristics of the architecture. It is shown that declustering retains the clustering advantage of avoiding IPC, yet overcomes the inflexibility associated with traditional clustering approaches.> Gilbert C. Sih, Edward A. Lee |
IEEE Trans. Parallel Distributed Syst. | 1 |
| 1990 | Scheduling to Account for Interprocessor Communication within Interconnection-Constrained Processor Networks
Gilbert C. Sih, Edward A. Lee |
ICPP (1) | 1 |