One popular technique to deal with increasing leakage current in modern FPGAs is to group logic into sleeper cells and isolate them from power rails whenever they are inactive in time and space. However, such architectures demand novel methodology to effectively layout the design, so that maximum sleeper cells can be shut down. In this work, we present a slicing tree based simulated annealing methodology that grooms the various blocks of a design, so that they can be put into power-down mode either in temporal or spatial domain. Our technique nicely fits into a power-aware design flow targeting standby/portable applications where substantial portion of the design sits idle for a long period of time. We also propose a novel technique to include BRAMs into the presented methodology. Our experiments shows up to a maximum 43% of leakage savings in some benchmarks

The linear algebraic approach to queuing theory is applied to analyze the performance of a typical single-bus multiprocessor system. This system can be modeled as an M/G/1/N queuing system with load-dependent arrivals. The method presented requires only that the nonexponential service time distribution for the system be a matrix-exponential, that is, one with a rational Laplace transform. Using linear algebraic techniques, expressions are obtained for the performance characteristics of interest, such as the processing power for the multiprocessor system. The algorithm does not rely on root finding and can be implemented using symbolic programming techniques. The explicit closed-form expression for the processing power is presented for some special cases.>