With advances in technology scaling and globalization of the semiconductor industry, the vulnerability of analog integrated circuits (ICs) to reverse-engineering-based attacks, intellectual property theft, and unauthorized access has increased. Prior state-of-the-art analog deobfuscation techniques, such as those using genetic algorithms (GAs) and the satisfiability modulo theory, require an Oracle (i.e., unlocked IC) to recover the correct key. However, in some scenarios, an attacker present in an untrusted foundry might not have access to the Oracle. We demonstrate an Oracle-less attack using Bayesian optimization (BO) to retrieve the key of locked analog designs. To thwart both Oracle-guided and Oracle-less attacks, we present an automated obfuscation circuit generation framework for securing analog ICs. By employing randomness in obfuscation circuit generation, the proposed analog key-based methodology safeguards the integrity and reliability of analog ICs. Experimental results and security analysis for several analog designs demonstrate the robustness of the proposed technique to optimization attacks based on a GA and BO. We further show that the probability of guessing the correct key through brute force attack for an obfuscated analog circuit is negligibly small$(4.83\times 10^{-18})$. The proposed obfuscation scheme incurs an area overhead of less than 1.3% and power overhead of less than 2.64% for a mixed-signal IC.

As the globalization of integrated circuits (ICs) continues to advance, the threat of hardware Trojans has emerged as a major concern in ensuring the security and reliability of analog circuits. While a considerable body of prior work has focused on detecting digital Trojans in digital circuits, the detection of analog Trojans in analog circuits has received significantly less attention. We present DAWN, a sensitivity analysis-based analog Trojan detection framework using neural networks to identify potential analog Trojan hotspots and prevent them from being exploited through unauthorized modifications. We incorporate circuit watermarks in these hotspots to provide an additional layer of security. With these watermarks, any malicious modification to the circuit is automatically detected with high accuracy. We target the detection of stealthy, large-delay Trojans that might be inserted either during the chip design or fabrication stages. Experimental results for analog benchmark circuits and two commonly studied analog Trojans demonstrate the effectiveness of the proposed framework.

In this paper, practical usage methodology of sampling technologies in industrial analog circuits is presented. We provide answers to common questions - e.g., how to select sample size, how to verify accuracy of sampling algorithms, and what savings may be achieved by using sampling technologies - by means of running a state-of-the-art commercial analog defect simulator on a few recently provided, industrial-sized analog circuits. We demonstrate our recommended flow and present results for a PLL, a SARADC, and a PHY circuit - with transistor counts ranging approximately between 3000 and 30000.

The growing size of analog IPs has made targeted structural testing of such designs a challenging problem. We present a gradient-based automated test generation framework for analog circuits using neural twins, which are neural equivalents of the corresponding analog circuit. A neural twin is constructed by combining several FET-twins that lie in the paths between the circuit's inputs and observation points. Each FET-twin is a fully-connected neural network that models the IV characteristics of individual MOSFETs in the design. We train different variants of FET-twins that can predict both the output current and nodal voltage with more than 99% accuracy. We create an analog neural miter circuit, for which tests are generated using gradient ascent to maximize the loss between the faulty and fault-free versions of the neural twin. By computing gradients in a batchwise fashion for all the faults in the design, we develop a test compaction scheme that covers all faults with minimum number of test patterns. The neural twin-driven test generation method is interpretable, faster to simulate through GPUs, and guarantees convergence through backpropagation. We demonstrate the effectiveness of this framework by generating tests for structural defects in analog benchmark circuits. We show that our method outperforms an existing black-box optimization method that can be repurposed for test generation.

The traditional body of literature on analog testing deals with propagation of faults to the output nets of the circuit. Often the set of detectable faults remains unsatisfactory because suitable stimuli cannot be found for propagating certain faults to the output. Existing technology supports capturing of the state of internal nets of a circuit, thereby enhancing the scope of detecting faults by observing their effect on internal nets. This approach is feasible only if the number of internal nets probed by the built-in test structure is very few. This paper presents a structured approach that identifies the sensitive nets, namely a well chosen small subset of internal nets that are affected by these faults. We utilize the speed of DC analysis and some common behavioral aspects of analog signals to find out this subset. We report dramatic improvement in fault coverage on several circuits including benchmarks.

Detection of faults in a mixed-signal SOC at the pre-silicon stage is a challenge, especially when it has substantial analog components. Given the time taken for simulating analog circuits, designing tests to detect faults in them is not a straightforward task. Achieving a high fault coverage without doing extensive time-consuming transient simulation of the circuit under test (CUT) has remained elusive in the analog and mixed-signal (AMS) domain. Unlike test generation approach for digital designs which leverage logical equivalence between faults, in analog circuits, there does not exist any notion of logical equivalence, and therefore each fault needs to be treated independently. In this paper, we propose to use a combination of DC operating point analysis and AC analysis of the CUT to identify equivalent faults in analog circuits. We also put forward a methodology of synthesizing inputs which will be able to detect the faults during post-silicon testing. Our studies reveal the effectiveness of this approach in identifying equivalent faults and achieving high fault coverage with considerably reduced computations. By using proposed methodology of fault classification and input signal synthesis, we have been able to achieve a high fault coverage where most of the detectable faults are successfully covered.

In this IP session, there will be 3 presentations focusing on functional testing and fault injection for automotive functional safety applications as well as a discussion on fault simulation and modeling for relevant analog test content. The 1stpresentation will discuss verification solutions that accelerate fault injection for diagnostic coverage to meet ASIL requirements. The 2ndpresentation discusses the use of focused random testing to achieve better functional coverage for automotive products. The 3rdpresentation will discuss the various challenges associated with analog fault coverage in the absence of standards and discusses approaches to address them.

This paper describes the incorporation of an accurate physics-based model of the resonant tunneling diode (RTD) into Berkeley SPICE version 3F5 and addresses the related direct current (dc) and transient convergence problems caused by the negative differential resistance (NDR) and the exponential nature of the device characteristics. To circumvent the de convergence problems, a new continuation technique using artificial parameter embedding and a current limiting algorithm are proposed. The studies made in this paper have shown that these techniques are superior to the in-built continuation methods of SPICE, such as Gmin-stepping and Source-stepping, for a large number of circuits of varying sizes. To improve transient convergence performance, the following three algorithms are added to SPICE: a modified forced-convergence algorithm, a new time-step adjustment algorithm, and a modified device voltage prediction algorithm.

In this paper, we present the description and evaluation of a novel physical design tool, BISRAMGEN, that can generate reconfigurable and fault-tolerant RAM modules. This tool designs a redundant RAM array with accompanying built-in self-test (BIST) and built-in self-repair (BISR) logic that can switch out faulty rows and switch in spare rows. Built-in self-repair causes significant improvement in reliability, production yield, and manufacturing cost of ASICs and microprocessors with embedded RAMs.

In this paper we present a method for prototyping circuits designed using resonant-tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) devices that can enable us to realize large-scale digital circuits with negative differential-resistance (NDR) devices. Our method is based on designing CMOS circuits which can emulate the current-voltage (I-V) characteristics of RTDs. We demonstrate the effectiveness of our scheme by means of simulation and fabrication of an NDR shift register circuit.

A novel physical design tool, BISRAMGEN, that generates layout geometries of parametrized built-in self-repairable SRAM modules, producing significant improvement in testability, reliability, production yield and manufacturing cost of ASICs and microprocessors with embedded RAMs, is presented.

Threshold gates consisting of RTDs in conjunction, with HBTs or CHFETs or MOS transistors can form extremely compact, ultrafast, digital logic alternatives. The resonant tunneling phenomenon causes these circuits to exhibit super-high-speed switching capabilities. Additionally, by virtue of being threshold logic gates, they are guaranteed to be more compact than traditional digital logic circuits while achieving the same functionality. However, reliable logic design with these gates will need a thorough understanding of their noise performance and power dissipation among other things. In this paper, we present an analytical study of the noise performance of these threshold gates supplemented by computer simulation results, with the objective of obtaining reliable circuit design guidelines.

Many semiconductor quantum devices utilize a novel tunneling transport mechanism that allows picosecond device switching speeds. The negative differential resistance characteristic of these devices, achieved due to resonant tunneling, is also ideally suited for the design of highly compact, self-latching logic circuits. As a result, quantum device technology is a promising emerging alternative for high-performance very-large-scale-integration design. The bistable nature of the basic logic gates implemented using resonant tunneling devices has been utilized in the development of a gate-level pipelining technique, called nanopipelining, that significantly improves the throughput and speed of pipelined systems. The advent of multiple-peak resonant tunneling diodes provides a viable means for efficient design of multiple-valued circuits with decreased interconnect complexity and reduced device count as compared to multiple-valued circuits in conventional technologies. This paper details various circuit design accomplishments in the area of binary and multiple-valued logic using resonant tunneling diodes (RTD's) in conjunction with high-performance III-V devices such as heterojunction bipolar transistors (HBT's) and modulation doped field-effect transistors (MODFET's). New bistable logic families using RTD+HBT and RTD+MODFET gates are described that provide a single-gate, self-latching majority function in addition to basic NAND, NOR, and inverter gates.