In this study, the mutual interference between two phase-locked loops (PLLs) was numerically analyzed by focusing on the electromagnetic coupling between the inductors. It was shown that the unstable state of the PLLs due to mutual interference, revealed in our previous theoretical work, can be reproduced by circuit simulation, and it was confirmed that the unstable coupling strength agrees well with the theoretical value. In addition, it was also clarified, through simulations using an electromagnetic field simulator, that the mutual coupling of inductors causes two PLLs at a certain distance to become unstable. Furthermore, to reduce mutual interference, a novel electromagnetic coupling mutual injection circuit was devised. A test circuit implementing the proposed circuit was designed using a 0.18$\mu \mathrm{m}$standard CMOS process.

The influence of coupling of oscillators in phase-locked loops (PLLs) was studied here. Particularly, numerical analyses based on nonlinear differential equations of the self- and mutual coupling systems were performed and compared with the results of the linear approximation model under synchronous conditions. The analysis revealed that coupling using the reference clock caused greater PLL instability than that caused by self-coupling for a given coupling strength. This shows that the phase error of mutual coupling exhibits the same behavior as that of reference-clock coupling in the single PLL under synchronous conditions, and the noise sensitivity of mutual coupling is twice that of the reference-clock coupling. In addition, the phase error of mutual coupling in the quasi-synchronous condition strongly depends on the relationship between the frequency difference of the two PLLs and the PLL bandwidth. We designed and fabricated the test circuits for theoretical verification using the 0.18-$\mu \text{m}$standard CMOS process. From the measurements, adjustment of the timing difference between the two PLLs is effective in mitigating mutual coupling under synchronous conditions. Moreover, we implemented mutual injections between two oscillators in the test circuit and confirmed their effectiveness. The proposed methods will be useful for achieving the compact and effective cancellation of the mutual coupling between PLLs.

The injection pulling of oscillators in phase-locked loop (PLL) circuits is analyzed by the linear approximation of nonlinear differential equations in terms of the oscillator phase. Applying this analysis to injection pulling in an injection-locked PLL (IL-PLL) and mutual injection between oscillators in a cascaded PLL, it is shown that the feedback loop becomes unstable due to the injection and the transfer function exhibits a large peak gain at the edge of the PLL bandwidth. These observations are confirmed by simulations based on linear model. It is also found that coupling from the second stage to the first stage can control the peak gain of transfer characteristics. Measurements on the test circuits of IL-PLL and cascaded PLL validate the proposed linear model. In particular, it reveals the dependence of jitter generation on the timing difference between the injection and oscillator. Additionally, in the cascaded PLL, it is shown that a properly controlled injection pulse mitigates the jitter generation caused by mutual injection pulling. This study presents important viewpoints on self and mutual interference in stand-alone and individual PLLs.

A time-interleaved analog-to-digital converter (TI-ADC) with voltage controlled oscillators (VCOs) is one promising candidate for ADCs in direct-RF sampling receivers. The VCO-based ADC, however, produces many harmonics due to the nonlinearity of the VCO gain, degrading the signal-to-noise-and-distortion ratio. We present a digital correction method for the third-order nonlinearity of TI-ADCs with VCOs in direct-RF sampling receivers dealing input signals centered at a quarter of the sampling frequency. Our method first estimates the nonlinearity with the cross-correlation function and adaptive signal processing of a third-order harmonic distortion (HD3) tone for a continuous wave (CW) signal. Then, it generates HD3and third-order intermodulation products for modulated signals to subtract them from the output of the receiver. This approach using the CW wave makes the correction circuit much simpler; it requires no lookup tables and auxiliary ADCs (VCOs). MATLAB/Simulink simulations show that the proposed method reduces an HD3tone from -49.8 dBc to -78 9 dBc for a CW signal and improves an error vector magnitude from 2.48% to 0.87% for a 16-QAM signal.

This paper deals with the educational scheme of PBL (project based learning), in which student groups build autonomous robotic vehicles for a competition game. In their scheme, students are split into 4 expert groups which consist of mechanism, actuator/power, sensor/communication, and embedded system groups. Students are given lectures in each group at first to be "experts", then form teams to build vehicles. One of the most challenging point is to provide appropriate tools for embedded system group because students (freshmen) are very beginner. For this purpose, the authors decided to employ "mbed" microcontroller development board and on-line development tools. In addition, studentes are given some fundamental function circuit boards such as motor driver board to build vehicle easily without soldering.This PBL was held as a lecture of nearly 400 students and its results are also discussed in this paper.

Cascaded integrator-comb (CIC) filters in a direct-RF sampling receiver reduce the quantization noise of an analog-to-digital converter (ADC) and out-of-band blockers being folded into the signal band. A higher order provides more attenuation for them but proportionally increases the power consumption and chip area. We present the procedure to determine the orders of a multistage CIC filter by using the analytical expressions of its output signal-to-noise ratio (SNR) and rejection in the signal band. The derived expressions first show a lower limit for the order to achieve the required SNR and then provide orders to satisfy the rejection requirements. A two-stage CIC filter consisting of 2nd- and 3rd-order CIC filters with a total decimation factor of 1024 is designed for a direct-RF sampling receiver complying with Bluetooth Low Energy (BLE) in MATLAB/Simulink. Simulations show that the CIC filter completely removes the folded quantization noise of a 2nd-order bandpass delta-sigma modulator and has a rejection of 63 dB for out-of-band blockers. The proposed procedure provides the lowest order of each CIC filter to enable the receiver to satisfy the SNR and out-of-band blocking requirements of BLE.

In this paper, we present a subharmonically injection-locked phase-locked loop (IL-PLL) with pulsed injection. When the pulsed injection signal is decomposed into its harmonics, we found that the oscillator responds only to the fundamental and harmonic elements of the oscillation frequency. The magnitude of these elements depends on the injection pulse width. Therefore, in order to increase the injection locking range, an adjustment of the injection pulse width is required. Compared with conventional pulsed injection, the bandwidth required by our pulse generator is reduced because the longer injection pulse width maintains the same injection-locking ability compared to the conventional injection pulse. We also investigate two specific injection methods, namely direct current injection and capacitive coupling injection, using theoretical analysis and circuit simulation. We design a test circuit of our proposed IL-PLL using a 0.18-μm standard CMOS process.