We present platform technology consisting of a scalable, low-power graphene field-effect transistor (GFET) array integrated with a custom neural interface system-on-chip (NISoC) for multiplexed biosensing. The platform features a$10 \times 10$GFET crossbar architecture with high-density channel integration and side-gated liquid sensing, enabling simultaneous detection of multiple bioanalytes in a compact footprint. Electrical characterization under varying phosphate-buffered saline (PBS) concentrations confirms stable Dirac point behavior and sensitivity to ionic strength, highlighting the system's electrostatic responsiveness. Integration with a low-power bioADCbased NISoC supports both current- and voltage-clamp operation, achieving sub-$\mu$W/channel power consumption. Currentclamp mode offers enhanced energy efficiency, critical for continuous monitoring in wearable applications. A streamlined graphene transfer process and dielectricisolated crossbar design ensure reproducible device performance across the array. The platform is being developed for surface functionalization with DNA aptamers to enable multiplexed biomarker detection in physiological fluids. These advancements position the system for real-time monitoring of health, stress, or disease markers in digital health and athletic performance settings. This work demonstrates a promising direction for next-generation wearable biosensors with low-power, high-density, and real-time signal acquisition capabilities.

Clo-HDnn is an on-device learning (ODL) accelerator designed for emerging continual learning (CL) tasks. Clo-HDnn integrates hyperdimensional computing (HDC) along with low-cost Kronecker HD Encoder and weight clustering feature extraction (WCFE) to optimize accuracy and efficiency. Clo-HDnn adopts gradient-free CL to efficiently update and store the learned knowledge in the form of class hypervectors. Its dual-mode operation enables bypassing costly feature ex- traction for simpler datasets, while progressive search reduces complexity by up to $61 \%$ by encoding and comparing only partial query hypervectors. Achieving 4.66 TFLOPS/W (FE) and 3.78 TOPS/W (classifier), Clo-HDnn delivers $7.77 \times$ and $4.85 \times$ higher energy efficiency compared to SOTA ODL accelerators.

Measuring the similarity of spike-trains is an essential operation for temporal neural coding, spike-based local learning rules, stereo vision and audio, for matching neuronal responses to their evoking stimuli, or for use as a loss function in supervised learning tasks in spiking neural networks. We present a novel spike-based temporal correlator and its accompanying analog subthreshold VLSI implementation, which can perform this operation accurately and efficiently. We discuss two potential applications of this primitive: (1) In event-based neuromorphic systems, it can be used to correlate spike-trains from multiple sources, e.g. pre- and post-synaptic spikes for spike-timing-dependent analog on-chip learning, or event-streams from multiple sensors like dynamic vision sensors and silicon cochleae for stereo-perception. (2) In (neuromorphic) neural interfaces the same framework can be used to correlate neural tissue activity with event-based stimuli, allowing us to identify the characteristic time-constant of the system, assuming integrative dynamics. We verify our results via schematic simulations in a 180nm process.

Ultra-wideband (UWB) communication and sensing, known for its high data rate and low latency, has emerged as a prominent technology in internet-of-things (IoT) and 5G communication applications. In this paper, we propose to utilize the Hadamard-Walsh Transformation (HWT) as an efficient and accurate channelization technique, in order to relax the per-channel receiver specifications. We present a comprehensive analysis of HWT and how it enables channelization, which is supported by simulation results. The study demonstrates HWT’s potential for applications such as RF analog-to-digital converter (ADC), correlator, and compressive sensing (CS).

Many demanding applications of signal processing and neural networks require scalable, precise and energy efficient matrix-vector multipliers. Translinear MOS circuits, which use logarithmically compressed subthreshold voltages to control linear currents, could offer a particularly dense solution with high dynamic range. However, their susceptibility to Process, Voltage and Temperature (PVT) variations has thus far hindered their use in large arrays. Therefore, we propose a scalable translinear matrix-vector multiplier array, comprising only two transistors and one capacitor per cell, that offers very high PVT invariance. We employ two techniques to achieve this: first, we use dynamic current mirroring within the individual multiplier cells. Second, we store the matrix coefficients using a correlated double sampling (CDS) scheme that is highly invariant to process and voltage variations. To improve retention, stored weights are periodically refreshed through the same CDS scheme, which also compensates for 1/f noise and temperature variations. This refresh is fast and row parallel, allowing our proposed array to scale to millions of weights. We designed and verified the proposed architecture through transistor-level simulation in a 22 nm CMOS process. At less than 0.5 fJ per multiply-accumulate operation, this architecture is especially promising for scalable low-power applications.

Many proposed in-memory-computing systems use analog memristive crossbars to compute matrix-vector products over discrete domains. This yields analog outputs distributed around discrete values across a wide nominal range. Lossless quantization of this range requires costly high-precision analog-to-digital converters (ADCs), which limits the applicability of this approach. But typical results are highly concentrated in a small central region; hence, an ADC with lower resolution that only operates in this central region can achieve almost full accuracy at a fraction of the cost. In this paper, we explore how to appropriately choose ADC resolution and the covered region of interest, specifically for low-precision applications in approximate in-memory-computing. Our results reveal two distinct strategies: ADCs with sufficient resolution should (at least) capture the region of interest without loss, whereas lower-resolution ADCs should space their levels just enough to cover the region of interest. We argue that using this scheme could drastically improve power efficiency and thus scalability of compute-in-memory architectures.

Understanding how the brain processes musical pitch errors is key to advancing music perception and auditory rehabilitation. This pilot study (N=1) examined neural responses to pitch deviations in a trained musician using a portable dry-electrode electroencephalography (EEG) system. The participant listened passively to seven 10-second violin excerpts with systematically varied pitch errors: none, medium, or high. EEG data were recorded, preprocessed, and analyzed for oscillatory patterns in the beta band across temporal and central brain regions. Findings revealed a graded increase in right-temporal beta power with error magnitude, alongside distinct temporal dynamics suggesting a sequential process: initial detection of deviations, evaluation of error severity, and adjustment of predictive models. These results highlight a potential cascade in passive pitch-error processing, extending prior work on active performance to naturalistic listening contexts. This work offers preliminary insights into the neural basis of pitch perception and suggests applications in music education and auditory training, though further research with larger cohorts is needed to confirm these findings.

Precise estimation of correlation or similarity between two random variables lies at the heart of signal detection, target localization and pattern recognition. In this paper, we show that there exists a large class of multiplier-less analog correlators that can demonstrate a higher signal-to-noise ratio (SNR) compared to a conventional multiply-accumulate (MAC) based correlator. The multiplier-less design uses a Margin Propagation (MP) principle combining rectifying diodes in a symmetric circuit architecture. Using Price’s theorem we present a novel analytical framework that can be used to understand the steady-state behavioral response of different MP correlator circuits. The analytical results have been verified using transient and steady-state circuit simulations of correlator circuits designed in a standard CMOS process.

One of the practical realizations of large-scale neuromorphic systems requires an area-efficient memristive crossbar array as a key building block supporting high-density synaptic connectivity. Conventional memristor-based AI accelerators rely on selector transistors to reduce sneak path-induced cross-talks, although other means can be equally effective. Removing the selector element on each memristor cross-point significantly improves array density (down to 4F2) and lowers power consumption. We present an integrated reconfigurable neuromorphic platform interfacing a selector-less 16x16 RRAM memristor crossbar array with peripheral row and column instrumentation for robust learning and inference with applications to AI on the edge. Bio-plausible local Hebbian-like incremental outer-product learning rules are mapped onto direct implementation across the memristive crossbar array, updated in a sequence of partial outer-product combinations presented at the periphery of the array. Our system provides a user-configurable platform to accommodate a broad spectrum of emerging non-volatile memory device technologies for synaptic crossbar arrays with embedded adaptive functionality for general AI and cognitive neuromorphic computing.

EEG continues to find a multitude of uses in both neuroscience research and medical practice, and independent component analysis (ICA) continues to be an important tool for analyzing EEG. A multitude of ICA algorithms for EEG decomposition exist, and in the past, their relative effectiveness has been studied. AMICA is considered the benchmark against which to compare the performance of other ICA algorithms for EEG decomposition. AMICA exposes many parameters to the user to allow for precise control of the decomposition. However, several of the parameters currently tend to be set according to “rules of thumb” shared in the EEG community. Here, 70-channel AMICA decompositions are run on data from a collection of participants while varying certain key parameters. The running time and quality of decompositions are analyzed based on two metrics, Pairwise Mutual Information (PMI) and Mutual Information Reduction (MIR), and derived recommendations for selecting parameter values are presented.

At the fundamental level, an energy imbalance exists between training and inference in machine learning (ML) systems. While inference involves recall using a fixed or learned set of parameters that can be energy-optimized using compression and sparsification techniques, training involves searching over the entire set of parameters and hence requires repeated memorization, caching, pruning, and annealing. In this paper, we introduce three “performance walls” that determine the training energy efficiency, namely, the memory-wall, the update-wall, and the consolidation-wall. While the emerging compute-in-memory ML architectures can address the memory-wall bottleneck (or energy-dissipated due to repeated memory access) the approach is agnostic to energy-dissipated due to the number and precision required for the training updates (the update-wall) and is agnostic to the energy-dissipated when transferring information between short-term and long-term memories (the consolidation-wall). To overcome these performance walls, we propose a learning-in-memory (LIM) paradigm that prescribes ML system memories with metaplasticity and whose thermodynamical properties match the physics and energetics of learning.

Memristive crossbar arrays have become essential building blocks in the realization of large-scale neuromorphic systems with high-density synaptic connectivity. Traditionally, memristor-based accelerators are equipped with selector elements to reduce cross-talk through sneak paths along unselected lines. However, due to the large drive strength required for selector elements, it comes at the cost of synaptic crossbar density. Selector- less alternatives require careful design of crossbar peripheral circuits to mitigate or eliminate sneak path-induced cross-talk. We propose a hybrid integrated platform that interfaces a selector- less memristor crossbar array with peripheral row and column instrumentation for array-parallel programming and readout for AI learning and inference applications. The proposed switched-capacitor voltage-sensing instrumentation avoids the need for current-sensing schemes with voltage-clamped sense lines that are typically used to mitigate the sneak path issues in selector- less crossbars but are substantially less energy-efficient than voltage-sensing. Our board-level platform is implemented using commercial off-the-shelf (COTS) data converters and switched capacitors, and is controlled by a Xilinx Spartan-6 FPGA. The system offers programmable sense times to characterize memristors over a wide range of resistances and the capability to switch between a transient-domain measurement and steady-state measurement to offer the desired trade-off between accuracy and energy efficiency during inference parallel readout. We implement a differential weight-encoding scheme to improve the accuracy of matrix-vector multiplication. The system also supports an array-level programming scheme for parallel write access as well as online learning-in-memory for neuromorphic applications through outer-product incremental decomposition of the weight matrix. Thus, our system offers a generic, user-configurable, and versatile platform to support wide dynamic range measurements of synaptic crossbar arrays and cognitive neuromorphic computing with emerging non-volatile memory devices.

Multiscale dynamics of neural and metabolic interactions implicated in disease states call for precision electrophysiology to resolve a variety of biopotential signals across the body that cover a wide range of frequencies, from the mHz-range electrogastrogram (EGG) to the kHz-range electroneurogram (ENG). Currently available integrated systems for unobtrusive and minimally invasive electrophysiology suffer from tradeoffs between bandwidth coverage, noise floor, power consumption, and input impedance, which limits their detection range and accuracy. Here we present a 16-channel wide-band ultra-low-noise neural recording system-on-chip fabricated in 65nm CMOS for chronic use in mobile healthcare settings that covers 0.001 Hz to 1 kHz bandwidth through sample-level duty-cycling. Each channel consists of a delta-sigma analog-to-digital converter (ADC) achieving$\mathbf{1.0}\ \mu \mathbf{V}_{rms}$input-referred noise over 1 Hz - 1 kHz bandwidth with a Noise Efficiency Factor (NEF) of 2.93 in continuous operation mode, while power duty-cycling of the biasing and clocks maintains consistent low input-referred noise levels down to 0.001 Hz sampling rates at$\mathbf{435}\ \mathbf{M}\Omega$input impedance. In vivo recordings from the chip interfacing to electrodes mounted on the forehead resolving slow-wave electroencephalogram (EEG) biopotentials demonstrate proof-of-concept functionality.

The field of design and design automation of micro-/nano-circuits and systems has played a pivotal role in advancing information technologies that are an inseparable part of all our lives. Without the fundamental principles and tools created in this field, modern-day electronic systems that form the foundations of today's information age would not be a reality. Though the field has achieved tremendous success in the past few decades, it is now facing some unprecedented challenges, stemming from foundational technologies all the way to new applications. Business-as-usual approaches are plateauing. New, fundamental research and innovation are needed to sustain the demanded growth. This paper aims to summarize the key challenges and future research directions in the field of micro/nano circuits and systems design and design automation.

State-of-the-art neuromorphic computing architectures to date suffer from interconnect scalability required for large-scale neural processing. We present a high-performance and low-overhead multicast network-on-chip (NoC) architecture for hierarchical address event routing (Multicast-HiAER) suitable for large-scale reconfigurable neuromorphic systems. Each building block of this efficient NoC architecture consists of several multi-cast advanced high-performance buses (mAHB) running in parallel for high-bandwidth inter-core spike event transmission. This architecture for scalable event routing can help to implement brain-scale sparse neural network connectivity distributed across neuromorphic processing cores, with network constraints typical of locally dense and globally sparse neuron connectivity. For a demonstration using a Xilinx Virtex Ultrascale VU37p FPGA, we have shown an $8\times 8$ grid of mAHBs running at 512MHz clock performing Level-1 and Leve1-2 inter-core communication at top bandwidth of 420M events per second per 128k neuron node in the hierarchy. This peak absolute bandwidth supports spike event registration with sub-ms latencies under worst-case conditions of all postsynaptic destinations being off-core.

To enable continuous, mobile health monitoring, body worn sensors need to offer comparable performance to clinical devices in a lightweight, unobtrusive package. This work presents a complete wireless electrophysiology data acquisition system (weDAQ) that is demonstrated for in-ear EEG with user-generic dry-contact electrodes made from standard printed circuit boards (PCBs). Each weDAQ device supports 16 channels, driven right leg, impedance scanning, 3-axis accelerometer data, local storage, high sampling rates, and adaptable data transmission modes. The weDAQ wireless platform supports body sensor networks (BSN) capable of aggregating multiple biosignal streams (EEG, EMG, EOG, etc.) by supporting simultaneous connectivity of multiple worn devices over the 802.11n WiFi protocol. Each channel achieves 28dB of gain over 70Hz bandwidth with a noise level of 0.92 μ Vpp and CMRR of 110.8 dB. In-ear and forehead EEG measurements taken from subjects captured modulation of alpha brain activity, EOG characteristic eye movements, and EMG from jaw muscles. The small footprint, performance, and flexibility of the weDAQ lay the foundation for online brain computer interface (BCI) experiments and smart, multimodal biosignal monitoring.

An asynchronous continuous-time level-crossing analog-to-digital converter (LC-ADC) for high-throughput, high-resolution applications is presented. The proposed 10-bit ADC architecture comprises two stages of level-crossing ADCs, the first stage resolving for 5 MSBs and the second folded residue stage for 5 LSBs. Gray encoding of the output bits ensure single-bit transitions between adjacent digital outputs. Compared to uniform-sampling synchronous ADCs, LC-ADCs generate fewer samples for sparse signals, useful in many applications for biomedical signal acquisition, event-driven computer vision, etc. Unlike conventional LC-ADCs with a few comparators tuned for lower power consumption to acquire sparse signals, this two-tier LC-ADC is optimized for high-resolution tracking of continuous signals, like Electrocardiogram (ECG). Designed and fabricated in 0.18-μm CMOS technology, chip area of the proposed ADC is 1310 × 125 μm2. Operating at 1.8 V supply, the ADC consumes 160-426 μW for 1 Hz to 200 kHz input frequencies at full scale amplitude and achieves an energy efficiency figure-of-merit of 4.16-pJ/conv.

Many recent generative models make use of neural networks to transform the probability distribution of a simple low-dimensional noise process into the complex distribution of the data. This raises the question of whether biological networks operate along similar principles to implement a probabilistic model of the environment through transformations of intrinsic noise processes. The intrinsic neural and synaptic noise processes in biological networks, however, are quite different from the noise processes used in current abstract generative networks. This, together with the discrete nature of spikes and local circuit interactions among the neurons, raises several difficulties when using recent generative modeling frameworks to train biologically motivated models. In this letter, we show that a biologically motivated model based on multilayer winner-take-all circuits and stochastic synapses admits an approximate analytical description. This allows us to use the proposed networks in a variational learning setting where stochastic backpropagation is used to optimize a lower bound on the data log likelihood, thereby learning a generative model of the data. We illustrate the generality of the proposed networks and learning technique by using them in a structured output prediction task and a semisupervised learning task. Our results extend the domain of application of modern stochastic network architectures to networks where synaptic transmission failure is the principal noise mechanism.

CMOS technology and its sustainable scaling have been the enablers for the design and manufacturing of computer architectures that have been fuelling a wider range of applications. Today, however, both the technology and the computer architectures are suffering from serious challenges/ walls making them incapable to deliver the right computing power at pre-defined constraints. This motivates the need of exploring new architectures and new technologies; not only to maintain the economic benefit of scaling, but also to enable the solutions of emerging computer power and data storage hungry applications such as big-data and data-intensive applications. This paper discusses the emerging memristor device as complementary (or alternative) to CMOS device and shows how this device can enable new ways of computing that will at least solve the challenges of today's architectures for some applications. The paper shows not only the potential of memristor devices in enabling new memory technologies and new logic design styles, but also their potential in enabling memory intensive architectures as well as neuromorphic computing due to their unique properties such as the tight integration with CMOS and the ability to learn and adapt.

Spike generation and routing is typically the most energy-demanding operation in neuromorphic hardware built using spiking neurons. Spiking neural networks running on neuromorphic hardware, however, often use rate-coding where the neurons spike rate is treated as the information-carrying quantity. Rate-coding is a highly inefficient coding scheme with minimal information content in each spike, which requires the transmission of a large number of spikes. In this paper, we describe an alternative type of spiking networks based on temporal coding where neuron spiking activity is very sparse and information is encoded in the time of each spike. We implemented the proposed networks on an FPGA platform and we use these sparsely active spiking networks to classify MNIST digits. The network FPGA implementation produces the classification output using only few tens of spikes from the hidden layer, and the classification result is obtained very quickly, typically within 1-3 synaptic time constants. We describe the idealized network dynamics and how these dynamics are adapted to allow an efficient implementation on digital hardware. Our results illustrate the importance of making use of the temporal dynamics in spiking networks in order to maximize the information content of each spike, which ultimately leads to reduced spike counts, improved energy efficiency, and faster response times.

In this paper we propose a method for continuously processing and learning from data in Restricted Boltzmann Machines (RBMs). Traditionally, RBMs are trained using Contrastive Divergence (CD), which is an algorithm consisting of two phases, of which only one is driven by data. This not only prohibits training of RBMs in conjugation with continuous-time data streams, especially in event-based real-time systems, but also hinders training speed of RBMs in large-scale machine learning systems. The model we propose trades space for time and, by pipelining information propagation in the network, is capable of processing both phases of the CD learning algorithm simultaneously. Simulation results of our model on generative and discriminative tasks show convergence to the original CD algorithm. We finalize with a discussion of applying our method to other deep neural networks, resulting in continuous learning and training time reduction.

Recent demand and initiatives in brain research have driven significant interest toward developing chronically implantable neural interface systems with high spatiotemporal resolution and spatial coverage extending to the whole brain. Electroencephalography-based systems are noninvasive and cost efficient in monitoring neural activity across the brain, but suffer from fundamental limitations in spatiotemporal resolution. On the other hand, neural spike and local field potential (LFP) monitoring with penetrating electrodes offer higher resolution, but are highly invasive and inadequate for long-term use in humans due to unreliability in long-term data recording and risk for infection and inflammation. Alternatively, electrocorticography (ECoG) promises a minimally invasive, chronically implantable neural interface with resolution and spatial coverage capabilities that, with future technology scaling, may meet the needs of recently proposed brain initiatives. In this paper, we discuss the challenges and state-of-the-art technologies that are enabling next-generation fully implantable high-density ECoG interfaces, including details on electrodes, data acquisition front-ends, stimulation drivers, and circuits and antennas for wireless communications and power delivery. Along with state-of-the-art implantable ECoG interface systems, we introduce a modular ECoG system concept based on a fully encapsulated neural interfacing acquisition chip (ENIAC). Multiple ENIACs can be placed across the cortical surface, enabling dense coverage over wide area with high spatiotemporal resolution. The circuit and system level details of ENIAC are presented, along with measurement results.

We present a hierarchical address-event routing (HiAER) architecture for scalable communication of neural and synaptic spike events between neuromorphic processors, implemented with five Xilinx Spartan-6 field-programmable gate arrays and four custom analog neuromophic integrated circuits serving 262k neurons and 262M synapses. The architecture extends the single-bus address-event representation protocol to a hierarchy of multiple nested buses, routing events across increasing scales of spatial distance. The HiAER protocol provides individually programmable axonal delay in addition to strength for each synapse, lending itself toward biologically plausible neural network architectures, and scales across a range of hierarchies suitable for multichip and multiboard systems in reconfigurable large-scale neuromorphic systems. We show approximately linear scaling of net global synaptic event throughput with number of routing nodes in the network, at $3.6\times 10^{7}$ synaptic events per second per 16k-neuron node in the hierarchy.

Capacitive non-contact electric field sensing is a prime modality for signal detection and communication in a variety of contexts ranging from bio-potential measurements and proximity sensing to body centered communication and human computer interaction. Although recent developments in the space of wearable sensors have greatly expanded the sensory capability, they simultaneously place more stringent requirements on the front-end. Thus, low-noise power efficient front-ends that can demonstrate low input parasitic capacitances can accelerate the adoption of sensing and communication technologies that exploit this form of capacitive coupling. To this end, we present results from a 193μm2, 6μW/MHz, unity-gain, charge buffer, fabricated in 65nm CMOS for use in electric field sensing.

Memristive devices have been shown to exhibit slow and stochastic resistive switching behavior under low-voltage, low-current operating conditions. Here we explore such mechanisms to emulate stochastic plasticity in memristor crossbar synapse arrays. Interfaced with integrate-and-fire spiking neurons, the memristive synapse arrays are capable of implementing stochastic forms of spike-timing dependent plasticity which parallel mean-rate models of stochastic learning with binary synapses. We present theory and experiments with spike-based stochastic learning in memristor crossbar arrays, including simplified modeling as well as detailed physical simulation of memristor stochastic resistive switching characteristics due to voltage and current induced filament formation and collapse.

Using a neural sampling approach, networks of stochastic spiking neurons, interconnected with plastic synapses, have been used to construct computational machines such as Restricted Boltzmann Machines (RBMs). Previous work towards building such networks achieved lower performances than traditional RBMs. More recently, Synaptic Sampling Machines (SSMs) were shown to outperform equivalent RBMs. In Synaptic Sampling Machines (SSMs), the stochasticity for the sampling is generated at the synapse. Stochastic synapses play the dual role of a regularizer during learning and an efficient mechanism for implementing stochasticity in neural networks over a wide dynamic range. In this paper we show that SSMs with stochastic synapses implemented in FPGA-based spiking neural networks can obtain a high accuracy in classifying MNIST handwritten digit database. We compare classification accuracy for different bit precision for stochastic and non-stochastic synapses and further argue that stochastic synapses have the same effect as synapses with higher bit precision but require significantly lower computational resources.

Restricted Boltzmann Machines and Deep Belief Networks have been successfully used in a wide variety of applications including image classification and speech recognition. Inference and learning in these algorithms uses a Markov Chain Monte Carlo procedure called Gibbs sampling. A sigmoidal function forms the kernel of this sampler which can be realized from the firing statistics of noisy integrate-and-fire neurons on a neuromorphic VLSI substrate. This paper demonstrates such an implementation on an array of digital spiking neurons with stochastic leak and threshold properties for inference tasks and presents some key performance metrics for such a hardware-based sampler in both the generative and discriminative contexts.

The human vision system understands and interprets complex scenes for a variety of visual tasks in real-time while consuming less than 20 Watts of power. The holistic design of artificial vision systems that will approach and eventually exceed the capabilities of human vision systems is a grand challenge. The design of such a system needs advances in multiple disciplines. This paper focuses on advances needed in the computational fabric and provides an overview of a new-genre of architectures inspired by advances in both the understanding of the visual cortex and the emergence of devices with new mechanisms for state computations.

Restricted Boltzmann Machines (RBMs) and Deep Belief Networks (DBNs) have been demonstrated to perform efficiently on a variety of applications, such as dimensionality reduction and classification. Implementation of RBMs on neuromorphic platforms, which emulate large-scale networks of spiking neurons, has significant advantages from concurrency and low-power perspectives. This work outlines a neuromorphic adaptation of the RBM, which uses a recently proposed neural sampling algorithm (Buesing et al. 2011), and examines its algorithmic efficiency. Results show the feasibility of such alterations, which will serve as a guide for future implementation of such algorithms in neuromorphic very large scale integration (VLSI) platforms.

Wearable, unobtrusive and patient friendly physiological sensors will be a key driving force in the wireless health revolution. Cardiac (ECG) and brain (EEG) signals are two important signal modalities indicative of healthy and diseased states of body and mind that directly benefit from long-term monitoring. Despite advancements in wireless and embedded electronics technology, however, ECG/EEG monitoring devices still face problems with patient compliance and comfort from the use wet/gel electrodes. We have developed two wireless biopotential instrumentation systems using noncontact electrodes that can operate without direct skin contact and through thin layers of fabric. The first system is a general purpose replacement for traditional ECG/EEG telemetry systems and the second is a compact, fully self-contained wireless ECG tag. All of the issues relating to the design of low noise, high performance noncontact sensors are discussed along with full technical details, circuit schematics and construction techniques. The noncontact electrode has been integrated into both a wearable ECG chest harness as well an EEG headband and characterized in a battery of experiments that represent potential health applications including resting ECG, exercise ECG and EEG directly against standard clinical adhesive Ag/AgCl electrodes. With careful design and secure mechanical harnesses the noncontact sensor is capable of approaching the quality of conventional electrodes.

This study proposes and evaluates a recursive algorithm for incremental estimation of independent components from on-line data. The algorithm offers the convergence properties of batch independent component analysis (ICA) with incremental updates of a form similar to natural gradient (NG) on-line information maximization (Infomax). We employ recursive procedure to arrive at steady state solution given by NG Infomax. Furthermore, we propose a novel procedure to compute corrective updates on the basis of previous estimates. Implementation of this algorithm incurs linear complexity in data size, input dimensions, and number of estimated independent components. Significant gains in convergence rate over on-line natural gradient ICA are demonstrated.

A multi-channel mixed-signal noise source with uniform amplitude distribution is presented. Cross-coupled, counter-propagating linear feedback shift registers are used to produce mutually independent binary distributed noises, which in turn generates mutually independent uniformly-distributed discrete-analog noises after digital-to-analog conversion. A stochastic comparator offset cancellation technique based on the proposed analog noise source is demonstrated. Applications include energy-efficient stochastic ADCs and high-density analog built-in self-test.

Recent advances in neuromorphic engineering for brain-like computing and neural prostheses are converging towards realization of electronic synaptic arrays approaching the integration density and energy efficiency of the human brain. A major impediment in this development is the real-time synaptic routing in a large-scale spiking neuron architecture. Here we present a hierarchical address-event routing (HiAER) communication architecture for routing neural events in a scaleable reconfigurable large-scale neuromorphic system. The neural events are routed in real-time through synaptic connections with configurable parameters governing connectivity, synaptic strength, and axonal delay. The HiAER architecture is implemented on a hardware platform with five Xilinx Spartan-6 FPGA cores.

Dry and non-contact electrodes are an important part of building user-friendly wearable body sensor networks for physiological (ECG, EEG, EMG) recording. This paper presents the theory and characterization of several inexpensive and non-irritating electrode materials that implement dry and non-contact sensors, including lead-free PCB solder finish, latex, cotton, silver cloth and solder mask. The noise spectra of the electrodes were measured on a live subject to fully mode all the effects of biological and chemical noise processes at the skin- electrode interface. In addition, exemplary ECG physiological measurements are also presented and compared against the signal from reference clinical wet Ag/AgCl electrodes. Results show that PCB finish can function as a general purpose, low-noise dry electrode. Latex and solder mask also work well as insulated electrodes.

People rarely put in their papers the things that didn't work, the mistakes they made, and how they found out what went wrong. Such confessions can help others learn how to avoid similar mistakes. Twenty-six confessions were collected to form the bulk of this paper. Themes that arise are errors that result from not understanding the limitations of simulation tools in modeling physical reality, chip verification errors that result from lack of clear communication between designers, and projects that are considered in their own isolated environment of technical challenges rather than the broader context of their environment or application.

A digitally controlled resonant tank oscillator with loop antenna radiating inductor offers high energy efficiency in BFSK transmission, however suffers from frequency drift. Here we present a fast-settling adaptive digital architecture for dual-loop frequency locking of a BFSK transmitter. The method uses interleaved frequency-locked loops (FLL) that allow fast and energy-efficient direct digitally controlled oscillator (DCO) frequency modulation at a data rate exceeding the settling time of the frequency adaptation, while maintaining frequency regulation. The fully digital FLL architecture retains the dual-loop adapted states between transmission bursts, allowing for energy efficient low duty cycle transmissions with minimal or no settling transient at the beginning of a transmission burst. Analysis and simulation results are presented of the architecture operating in the 402-405 MHz MICS band for biomedical applications, indicating locking at 130 kHz frequency resolution at 115 μs settling for 125 kbps BFSK telemetry.

A wireless EEG/ECG system using non-contact sensors is presented. The system consists of a set of simple capacitive electrodes manufactured on a standard printed circuit board that can operate through fabric or other insulation. Each electrode provides 46 dB of gain over a .7-100 Hz bandwidth with a noise level of 3.80μV RMS for high quality brain and cardiac recordings. Signals are digitized directly on top of the electrode and transmitted in a digital serial daisy chain, minimizing the number of wires required on the body. A small wireless base unit transmits EEG/ECG telemetry to a computer for storage and processing.

We present a high-speed CMOS active pixel sensor (APS) image sensor with focal plane histogram computation. The 128×128 4-transistor active pixel sensor array produces cumulative intensity histograms, at the focal-plane, with speeds in excess of 10,000 frames per second for low-latency, realtime control applications without the need for pixel digitization of external processing. In addition, an on-chip 10-bit column parallel analog-to-digital converter with a read noise of 0.6LSB and negligible fixed pattern noise facilitates conventional imaging operations and data acquisition. Each pixel occupies 19.5μm×19.5μm with a fill factor of 43%. Power consumption is 1.5mW during imaging mode and 4.6mW in high-speed histogram mode. Applications include real-time adaptive optics control for laser communications.

We present a compact circuit architecture for analog VLSI realization of event-addressable neuromorphic arrays with conductance-based synaptic dynamics. Synaptic input events are time-multiplexed, pooled by synapse type according to common reversal potential and activation dynamics. One such physical synapse element per postsynaptic neuron is provided for each type, selected by type index along with postsynaptic address. A log-domain encoding of first-order linear dynamics of synaptic conductance results in a compact circuit realization with three MOS transistors per synapse element. Circuit simulations show low-power operation with linear dynamics in conductance.

This paper presents a 128 times 128 charge-mode CMOS imaging sensor that computes separable transforms directly on the focal plane. The pixel is a unique extension of the widely reported active pixel sensor (APS) cell. By capacitively coupling across an array of such cells onto switched capacitor circuits, computation of any unitary 2-D transform that is separable into inner and outer products is possible. This includes the Walsh, Hadamard and Haar basis functions. This scheme offers several advantages including multiresolution imaging, inherent de-noising, compressive sampling and lower integration voltage and faster readout. The chip was implemented on a 0.5 mum CMOS process and measures 9 mm2in MOSIS' submicron design rules.

We demonstrate neuron spiking dynamics in a small network of analog silicon neurons with dynamical conductance-based synapses. The analog VLSI chip (NeuroDyn) emulates analog continuous-time dynamics in a fully digitally programmable network of 4 biophysical neurons. Each neuron in NeuroDyn implements Hodgkin-Huxley dynamics in 4 variables, with 28 parameters defining the conductances, reversal potentials, and voltage-dependence of the channel kinetics. All 12 chemical synapses interconnecting the neurons also have individually programmable parameters defining conductance, reversal potential, and pre/post-synaptic voltage dependence of the channel kinetics. All configurable parameters in the implemented model have a biophysical origin, thus supporting direct interpretation of the results of adapting/tuning the parameters in terms of neurobiology. Uniform temporal scaling of the dynamics of membrane and gating variables is demonstrated by tuning a single current parameter, yielding variable speed output exceeding real time. The 0.5 mum CMOS chip measures 3 mm times 3 mm, and consumes 1.29 mW.

An image sensor with focal plane based hardware acceleration of video compression is presented. The 90 x 90 pixel CMOS image sensor provides in-pixel professing of intensity changes, serving as an analog memory and processor for temporal image difference computation. Surveillance quality videos of up to a 48:1 compression ratio via a temporally compensated DCT based compression algorithm is attained with just an 18.5 MHz micro-controller. Power consumption is 225 mW during full operation and 6mVV during full sleep mode that continuously monitors for change events to trigger encoding.

We demonstrate dynamic power maximization and synchronization of a wireless RF communication link through adaptation of the radiation pattern of a phased array at the transmitter. Adaptation is performed through a multi-dithering, coherent detection gradient descent analog controller chip, and compensates for phase variations in the communication link. The chip, located at the transmitter, controls the phase of each element in the array so that all transmitted signals combine coherently in phase at the receiver. The control objective is the downconverted RF signal at the receiver, which is fed back to the input of the chip through a reverse, lower bandwidth analog RF link. Measurements on the demonstrated prototype, consisting of a 4-element phased array at the transmitter and an omnidirectional receiver, indicate microsecond scale continuous-time optimization of the system.

Recently, a delay-insensitive architecture for gradient descent adaptive control, based on parallel synchronous detection for model-free gradient estimation was presented. The key to delay insensitivity in the gradient estimation is careful selection of the phase of the local oscillator in the mixer of synchronous detection, amounting to a single parameter to be estimated per control channel. In this contribution we present a practical adaptive phase selection algorithm for delay compensation in the adaptive control architecture, and present experimental results from a SiGe BiCMOS implementation of the architecture demonstrating sub-microsecond response time in closed-loop adaptive control.

A fully differential translinear 3-phase sinusoidal oscillator architecture is presented. The architecture is meant for BiCMOS implementation and uses only NPN devices, typically of higher performance than their PNP counterparts in most technologies. The architecture features both frequency and amplitude control and expressions are derived showing the dependence of these controls to external current biases. Measurements on a 0.5 mum SiGe BiCMOS implementation of the architecture demonstrate frequency control from below 80 Hz to above 800 MHz, general agreement between theory and actual data for the amplitude of oscillation, as well as low distortion. Power consumption scales with the frequency of operation and amounts to ~2 muW/MHz.

Electroencephalograph (EEG) recording systems offer a versatile, non-invasive window on the brain’s spatiotemporal activity for many neuroscience and clinical applications. Our research aims to improve the convenience and mobility of EEG recording by eliminating the need for conductive gel and creating sensors that fit into a scalable array architecture. The EEG drycontact electrodes are created with micro-electrical-mechanical system (MEMS) technology. Each channel of our analog signal processing front-end comes on a custom-built, dime-sized circuit board which contains an amplifier, filters, and analog-to-digital conversion. A daisy-chain configuration between boards with bitserial output reduces the wiring needed. A system consisting of seven sensors is demonstrated in a real-world setting. Consuming just 3 mW, it is suitable for mobile applications. The system achieves an input-referred noise of 0.28 μVrms in the signal band of 1 to 100 Hz, comparable to the best medical-grade systems in use. Noise behavior across the daisychain is characterized, alpha-band rhythms are detected, and an eye-blink study is demonstrated.

An ultra low power, low bandwidth wireless video sensor network is presented. Each wireless node includes a 90 by 90 CMOS image sensor node with focal plane temporal intensity change detection. As output, the camera provides not only the image intensity, but a digital flag indicating the presence and direction of change, thereby resulting in significant reductions in the amount of external memory and processing power necessary required for operation. Several compression schemes have been developed that take advantage of the change difference signaling from a pixel update wake up mode to a full motion DCT macroblock based scheme. Under typical surveillance scenarios, the temporal change encoding provides up to a twenty fold compression. The sensors have been successfully integrated with a ad-hoc wireless networking system.

A mixed-signal architecture for continuous-time multidimensional model-free optimization is presented. It is based on multi-channel coherent modulation and detection that reliably estimates the objective function's gradient, with respect to the system parameters, in the presence of time delays. The narrowband nature of the excitation signals reduces the unknown dynamics of the objective function to a single parameter per control channel, the phase delay. An efficient implementation of the adaptive control architecture is presented; it incorporates parallel control channels with individually selectable 6-level phase delay adjustment. Initial experimental results indicate wide operating range covering almost 7 decades of excitation frequencies.

We present a multichip, mixed-signal VLSI system for spike-based vision processing. The system consists of an 80 x 60 pixel neuromorphic retina and a 4800 neuron silicon cortex with 4,194,304 synapses. Its functionality is illustrated with experimental data on multiple components of an attention-based hierarchical model of cortical object recognition, including feature coding, salience detection, and foveation. This model exploits arbitrary and reconfigurable connectivity between cells in the multichip architecture, achieved by asynchronously routing neural spike events within and between chips according to a memory-based look-up table. Synaptic parameters, including conductance and reversal potential, are also stored in memory and are used to dynamically configure synapse circuits within the silicon neurons.

The performance of speech recognition systems depends on consistent quality of the speech features across variable environmental conditions encountered during training and evaluation. This paper presents a kernel-based nonlinear predictive coding procedure that yields speech features which are robust to nonstationary noise contaminating the speech signal. Features maximally insensitive to additive noise are obtained by growth transformation of regression functions that span a reproducing kernel Hilbert space (RKHS). The features are normalized by construction and extract information pertaining to higher-order statistical correlations in the speech signal. Experiments with the TI-DIGIT database demonstrate consistent robustness to noise of varying statistics, yielding significant improvements in digit recognition accuracy over identical models trained using Mel-scale cepstral features and evaluated at noise levels between 0 and 30-dB signal-to-noise ratio.

A mixed-signal very large scale integration (VLSI) chip for large scale emulation of spiking neural networks is presented. The chip contains 2400 silicon neurons with fully programmable and reconfigurable synaptic connectivity. Each neuron implements a discrete-time model of a single-compartment cell. The model allows for analog membrane dynamics and an arbitrary number of synaptic connections, each with tunable conductance and reversal potential. The array of silicon neurons functions as an address-event (AE) transceiver, with incoming and outgoing spikes communicated over an asynchronous event-driven digital bus. Address encoding and conflict resolution of spiking events are implemented via a randomized arbitration scheme that ensures balanced servicing of event requests across the array. Routing of events is implemented externally using dynamically programmable random-access memory that stores a postsynaptic address, the conductance, and the reversal potential of each synaptic connection. Here, we describe the silicon neuron circuits, present experimental data characterizing the 3 mm x 3 mm chip fabricated in 0.5-microm complementary metal-oxide-semiconductor (CMOS) technology, and demonstrate its utility by configuring the hardware to emulate a model of attractor dynamics and waves of neural activity during sleep in rat hippocampus.

A robust system architecture to achieve optical coherency in multiple-beam free-space laser communication links with adaptive optics is introduced. It is based on deterministic multi-dithering and gradient descent flows and accounts for phase delays in the dither signal, during propagation in the atmosphere, as well as saturation of the optical phase shifters. The architecture has been mathematically analyzed and simulation results of a VLSI implementation of the architecture are presented and found in agreement with the theoretical model

A new central pattern generator chip with 24 silicon neurons and reprogrammable connectivity is presented. The 3mm /spl times/ 3mm chip fabricated in a 3M2P 0.5/spl mu/m process contains 1032 synapses, each with multiple floating gates for storing parameters governing synaptic strength and polarity. Every neuron includes a dendritic compartment with 12 externally-addressable synaptic inputs and 24 recurrent synaptic inputs, enabling construction of a fully-interconnected network with sensory feedback from off-chip elements. In addition to describing the chip architecture and neuron circuits, preliminary results from single oscillating neurons and pairs of phase-locked neurons are shown. This work represents the realization of a design presented at ISCAS'05, and an improvement over our 2nd generation CPG chip presented at ISCAS'04.

We present micropower mixed-signal VLSI hardware for real-time blind separation and localization of acoustic sources. Gradient flow representation of the traveling wave signals acquired over a miniature (1cm diameter) array of four microphones yields linearly mixed instantaneous observations of the time-differentiated sources, separated and localized by independent component analysis (ICA). The gradient flow and ICA processors each measure 3mm 3mm in 0.5 m CMOS, and consume 54 W and 180 W power, respectively, from a 3 V supply at 16 ks/s sampling rate. Experiments demonstrate perceptually clear (12dB) separation and precise localization of two speech sources presented through speakers positioned at 1.5m from the array on a conference room table. Analysis of the multipath residuals shows that they are spectrally diffuse, and void of the direct path.

A robust speech feature extraction procedure, by kernel regression nonlinear predictive coding, is presented. Features maximally insensitive to additive noise are obtained by growth transformation of regression functions spanning a reproducing kernel Hilbert space (RKHS). Experiments on TI-DIGIT demonstrate consistent robustness of the new features to noise of varying statistics, yielding significant improvements in digit recognition accuracy over identical models trained using Mel-scale cepstral features and evaluated at noise levels between 0 and 30 dB SNR.

An auditory perception model for noise-robust speech feature extraction is presented. The model assumes continuous-time filtering and rectification, amenable to real-time, low-power analog VLSI implementation. A 3 mm/spl times/3 mm CMOS chip in 0.5 /spl mu/m CMOS technology implements the general form of the model with digitally programmable filter parameters. Experiments on the TI-DIGIT database demonstrate consistent robustness of the new features to noise of various statistics, yielding significant improvements in digit recognition accuracy over models identically trained using Mel-scale frequency cepstral coefficient (MFCC) features.

An analog system-on-chip for kernel-based pattern classification and se- quence estimation is presented. State transition probabilities conditioned on input data are generated by an integrated support vector machine. Dot product based kernels and support vector coefficients are implemented in analog programmable floating gate translinear circuits, and probabil- ities are propagated and normalized using sub-threshold current-mode circuits. A 14-input, 24-state, and 720-support vector forward decod- ing kernel machine is integrated on a 3mm3mm chip in 0.5m CMOS technology. Experiments with the processor trained for speaker verifica- tion and phoneme sequence estimation demonstrate real-time recognition accuracy at par with floating-point software, at sub-microwatt power. 1 Introduction The key to attaining autonomy in wireless sensory systems is to embed pattern recognition intelligence directly at the sensor interface. Severe power constraints in wireless integrated systems incur design optimization across device, circuit, architecture and system levels [1]. Although system-on-chip methodologies have been primarily digital, analog integrated sys- tems are emerging as promising alternatives with higher energy efficiency and integration density, exploiting the analog sensory interface and computational primitives inherent in device physics [2]. Analog VLSI has been chosen, for instance, to implement Viterbi [3] and HMM-based [4] sequence decoding in communications and speech processing. Forward-Decoding Kernel Machines (FDKM) [5] provide an adaptive framework for gen- eral maximum a posteriori (MAP) sequence decoding, that avoid the need for backward recursion over the data in Viterbi and HMM-based sequence decoding [6]. At the core of FDKM is a support vector machine (SVM) [7] for large-margin trainable pattern classifi- cation, performing noise-robust regression of transition probabilities in forward sequence estimation. The achievable limits of FDKM power-consumption are determined by the number of support vectors (i.e., regression templates), which in turn are determined by the complexity of the discrimination task and the signal-to-noise ratio of the sensor inter- face [8]. MVM MVM 24 2 1 SUPPORT VECTORS KERNEL s x s i1 30x24 30x24 K(x,x s ) x f (x) 14 24x24 i1 INPUT NORMALIZATION P P i1 i24 24x24 24 FORWARD DECODING j[n-1] 24 i[n] Figure 1: FDKM system architecture. In this paper we describe an implementation of FDKM in silicon, for use in adaptive se- quence detection and pattern recognition. The chip is fully configurable with parameters directly downloadable onto an array of floating-gate CMOS computational memory cells. By means of calibration and chip-in-loop training, the effect of mismatch and non-linearity in the analog implementation is significantly reduced. Section 2 reviews FDKM formulation and notations. Section 3 describes the schematic details of hardware implementation of FDKM. Section 4 presents results from experiments conducted with the fabricated chip and Section 5 concludes with future directions. 2 FDKM Sequence Decoding FDKM recognition and sequence decoding are formulated in the framework of MAP (max- imum a posteriori) estimation, combining Markovian dynamics with kernel machines. The MAP forward decoder receives the sequence X[n] = {x[1], x[2], . . . , x[n]} and pro- duces an estimate of conditional probability measure of state variables q[n] over all classes i 1, .., S, i[n] = P (q[n] = i | X[n]). Unlike hidden Markov models, the states directly encode the symbols, and the observations x modulate transition probabilities be- tween states [6]. Estimates of the posterior probability i[n] are obtained from estimates of local transition probabilities using the forward-decoding procedure [6] S P i[n] = ij [n] j [n - 1] (1) j=1 where Pij[n] = P (q[n] = i | q[n - 1] = j, x[n]) denotes the probability of making a transition from class j at time n - 1 to class i at time n, given the current observation vector x[n]. Forward decoding (1) expresses first order Markovian sequential dependence of state probabilities conditioned on the data. The transition probabilities Pij[n] in (1) attached to each outgoing state j are obtained by normalizing the SVM regression outputs fij(x): Pij[n] = [fij(x[n]) - zj[n]]+ (2) Vdd M4 A V V g ref g V M1 V M2 c c M3 C B V V I tunn tunn out Iin (a) (x.x )2 Vdd s x M7 M9 M10 M8 Vbias M5 M6 (b) sK(x, x ) ij s Figure 2: Schematic of the SVM stage. (a) Multiply accumulate cell and reference cell for the MVM blocks in Figure 1. (b) Combined input, kernel and MVM modules. where [.]+ = max(., 0). The normalization mechanism is subtractive rather than divisive, with normalization offset factor zj[n] obtained using a reverse-waterfilling criterion with respect to a probability margin [10], [fij(x[n]) - zj[n]]+ = . (3) i Besides improved robustness [8], the advantage of the subtractive normalization (3) is its amenability to current mode implementation as opposed to logistic normalization [11] which requires exponentiation of currents. The SVM outputs (margin variables) fij(x) are given by: N f s K ij (x) = (x, x ij s) + bij (4) s where K(, ) denotes a symmetric positive-definite kernel1 satisfying the Mercer condi- tion, such as a Gaussian radial basis function or a polynomial spline [7], and xs[m], m = 1, .., N denote the support vectors. The parameters s in (4) and the support vectors x ij s[m] are determined by training on a labeled training set using a recursive FDKM procedure de- scribed in [5]. 3 Hardware Implementation A second order polynomial kernel K(x, y) = (x.y)2 was chosen for convenience of im- plementation. This inner-product based architecture directly maps onto an analog compu- tational array, where storage and computation share common circuit elements. The FDKM 1K(x, y) = (x).(y). The map () need not be computed explicitly, as it only appears in inner-product form. f [n] Vdd Vdd Vdd Vdd ij i[n] M6 M9 Aij P [n] ij M7 M8 M4 M2 M3 M5 M1 Vref j[n-1] Figure 3: Schematic of the margin propagation block. system architecture is shown in Figure 1. It consists of several SVM stages that generates state transition probabilities Pij[n] modulated by input data x[n], and a forward decoding block that performs maximum a posteriori (MAP) estimation of the state sequence i[n].

We have constructed a system that uses an array of 9,600 spiking sili- con neurons, a fast microcontroller, and digital memory, to implement a reconfigurable network of integrate-and-fire neurons. The system is designed for rapid prototyping of spiking neural networks that require high-throughput communication with external address-event hardware. Arbitrary network topologies can be implemented by selectively rout- ing address-events to specific internal or external targets according to a memory-based projective field mapping. The utility and versatility of the system is demonstrated by configuring it as a three-stage network that accepts input from an address-event imager, detects salient regions of the image, and performs spatial acuity modulation around a high-resolution fovea that is centered on the location of highest salience.

A robust and accurate image recognizer for cephalometric landmarking is presented. The recognizer uses Gini support vector machine (SVM) to model discrimination boundaries between different landmarks and also between the background frames. Large margin classification with non-linear kernels allows to extract relevant details from the landmarks, approaching human expert levels of recognition. In conjunction with projected principal-edge distribution (PPED) representation as feature vectors, GiniSVM is able to demonstrate more than 95% accuracy for landmark detection on medical cephalograms within a reasonable location tolerance value.

A robust and accurate image recognizer for cephalometric landmarking is presented. The recognizer uses Gini support vector machine (SVM) to model discrimination boundaries between different landmarks and also between the background frames. Large margin classification with non-linear kernels allows to extract relevant details from the landmarks, approaching human expert levels of recognition. In conjunction with projected principal-edge distribution (PPED) representation as feature vectors, GiniSVM. is able to demonstrate more than 95% accuracy for landmark detection on medical cephalograms within a reasonable location tolerance value.

The objective of machine learning is to identify a model that yields good generalization performance. This involves repeatedly selecting a hypothesis class, searching the hypothesis class by minimizing a given objective function over the model's parameter space, and evaluating the generalization performance of the resulting model. This search can be computationally intensive as training data continuously arrives, or as one needs to tune hyperparameters in the hypothesis class and the objective function. In this paper, we present a framework for exact incremental learning and adaptation of support vector machine (SVM) classifiers. The approach is general and allows one to learn and unlearn individual or multiple examples, adapt the current SVM to changes in regularization and kernel parameters, and evaluate generalization performance through exact leave-one-out error estimation.

Training of support vector machines (SVMs) amounts to solving a quadratic programming problem over the training data. We present a simple on-line SVM training algorithm of complexity approximately linear in the number of training vectors, and linear in the number of support vectors. The algorithm implements an on-line variant of sequential minimum optimization (SMO) that avoids the need for adjusting select pairs of training coefficients by adjusting the bias term along with the coefficient of the currently presented training vector. The coefficient assignment is a function of the margin returned by the SVM classifier prior to assignment, subject to inequality constraints. The training scheme lends efficiently to dedicated SVM hardware for real-time pattern recognition, implemented using resources already provided for run-time operation. Performance gains are illustrated using the Kerneltron, a massively parallel mixed-signal VLSI processor for kernel-based real-time video recognition.

Detection of complex objects in streaming video poses two fundamental challenges: training from sparse data with proper generalization across variations in the object class and the environment; and the computational power required of the trained classifier running real-time. The Kerneltron supports the generalization performance of a support vector machine (SVM) and offers the bandwidth and efficiency of a massively parallel architecture. The mixed-signal very large-scale integration (VLSI) processor is dedicated to the most intensive of SVM operations: evaluating a kernel over large numbers of vectors in high dimensions. At the core of the Kerneltron is an internally analog, fine-grain computational array performing externally digital inner-products between an incoming vector and each of the stored support vectors. The three-transistor unit cell in the array combines single-bit dynamic storage, binary multiplication, and zero-latency analog accumulation. Precise digital outputs are obtained through oversampled quantization of the analog array outputs combined with bit-serial unary encoding of the digital inputs. The 256 input, 128 vector Kerneltron measures 3 mm/spl times/3mm in 0.5 /spl mu/m CMOS, delivers 6.5 GMACS throughput at 5.9 mW power, and attains 8-bit output resolution.

Real-time classification of objects from active sonar echo-location requires a tremendous amount of computation, yet bats and dolphins perform this task effortlessly. To bridge the gap between human-engineered and biosonar system performance, we developed special-purpose hardware tailored to the parallel distributed nature of the computation performed in biology. The implemented architecture contains a cochlear filterbank front-end performing time-frequency feature extraction, and a kernel-based neural classifier for object detection. Based on analog programmable components, the front-end can be configured as a parallel or cascaded bandpass filterbank of up to 34 channels spanning the 10 to 150 kHz range. The classifier is implemented with the Kerneltron, a massively parallel mixed-signal Support Vector “Machine” in silicon delivering a throughput in excess of a trillion (1012) multiply-accumulates per second for every Watt of power dissipation. The system has been evaluated on detection of mine-like objects using linear frequency modulation active sonar data (LFM2, CSS Panamy City), achieving an out-or-sample performance of 93% correct single-ping detection at 5% false positives, and a real-time throughput of 250 pings per second.

A forward decoding approach to kernel machine learning is presented. The method combines concepts from Markovian dynamics, large margin classifiers and reproducing kernels for robust sequence detection by learning inter-data dependencies. A MAP (maximum a posteriori) sequence estimator is obtained by regressing transition probabilities between symbols as a function of received data. The training procedure involves maximizing a lower bound of a regularized cross-entropy on the posterior probabilities, which simplifies into direct estimation of transition probabilities using kernel logistic regression. Applied to channel equalization, forward decoding kernel machines outperform support vector machines and other techniques by about 5dB in SNR for given BER, within 1 dB of theoretical limits.

Gradient flow converts the problem of separating unknown delayed mixtures of sources, from traveling waves impinging on .an array of sensors, into a simpler problem of separating unknown instantaneous mixtures of the time-differentiated sources, obtained by acquiring or computing spatial and temporal derivatives on the array. The linear coefficients in the instantaneous mixture directly represent the delays, which in tum determine the direction angles of the sources. This formulation is attractive, since it allows to separate and localize waves of broadband signals using standard tools of independent component analysis (ICA), yielding the sources along with their direction angles. The technique is suited for arrays of small aperture, with dimensions shorter than the coherence length of the waves. We present gradient flow experiments on an array of four hearing aid microphones placed within a 5 mm radius, yielding 20 dB separation of joint speech in outdoors acoustic environments, and 10 dB separation indoors under mild reverberant conditions. These results suggest applications of gradient flow miniature microphone arrays to intelligent hearing aids with adaptive suppression of interfering signals and nonstationary noise.

Forward decoding kernel machines (FDKM) combine large-margin clas(cid:173) sifiers with hidden Markov models (HMM) for maximum a posteriori (MAP) adaptive sequence estimation. State transitions in the sequence are conditioned on observed data using a kernel-based probability model trained with a recursive scheme that deals effectively with noisy and par(cid:173) tially labeled data. Training over very large data sets is accomplished us(cid:173) ing a sparse probabilistic support vector machine (SVM) model based on quadratic entropy, and an on-line stochastic steepest descent algorithm. For speaker-independent continuous phone recognition, FDKM trained over 177 ,080 samples of the TlMIT database achieves 80.6% recognition accuracy over the full test set, without use of a prior phonetic language model.

Address-event representation (AER), originally proposed as a means to communicate sparse neural events between neuromorphic chips, has proven efficient in implementing large-scale networks with arbitrary, configurable synaptic connectivity. In this work, we further extend the functionality of AER to implement arbitrary, configurable synaptic plas- ticity in the address domain. As proof of concept, we implement a bi- ologically inspired form of spike timing-dependent plasticity (STDP) based on relative timing of events in an AER framework. Experimen- tal results from an analog VLSI integrate-and-fire network demonstrate address domain learning in a task that requires neurons to group corre- lated inputs.

A mixed-signal paradigm is presented for high-resolution parallel inner- product computation in very high dimensions, suitable for efficient im- plementation of kernels in image processing. At the core of the externally digital architecture is a high-density, low-power analog array performing binary-binary partial matrix-vector multiplication. Full digital resolution is maintained even with low-resolution analog-to-digital conversion, ow- ing to random statistics in the analog summation of binary products. A random modulation scheme produces near-Bernoulli statistics even for highly correlated inputs. The approach is validated with real image data, and with experimental results from a CID/DRAM analog array prototype in 0.5

We develop stochastic adaptive algorithms for on-line correction of spatial nonuniformity in random-access addressable imaging systems. The adaptive architecture is implemented in analog VLSI, integrated with the sensors on the focal plane. Random sequences of address locations selected with predetermined statistics are used to adaptively equalize the intensity distribution at a variable spatial scale. Through a logarithm transformation of system variables, adaptive gain correction is achieved through offset correction in the log-domain. This idea is particularly attractive for compact implementation using translinear floating-gate MOS circuits. The technique applies to a variety of solid-state imagers, such as artificial retinas and IR sensor arrays. Experimental results confirm gain correction in a 64/spl times/64 pixel adaptive array integrated on a 2.2 mm/spl times/2.25 mm chip in 1.2 /spl mu/m CMOS technology.

We present a mixed-signal VLSI architecture for state-parallel analog Viterbi decoding, including an analog Add-Compare-Select (ACS) module and a digital survivor path memory (PM) module. A single-chip 64-state analog Viterbi decoder for K=7 convolutional code has been implemented in 3.3 V 0.5 /spl mu/m CMOS technology. The chip measures 5.05/spl times/2.54 mm/sup 2/, and achieves a decoding speed of 40 Mb/s (20 MHz clock) at 50 mW power consumption as verified by post-layout transistor-level simulation. In addition, a behavioral model accounting for inaccuracies in the analog implementation is developed to simulate the bit error rate (BER) vs. signal-to-noise (SNR) performance, confirming superior error correction (coding gain) of the mixed-signal design over hard-decision and 3-bit soft-decision digital implementations.

We have designed a CMOS integrated circuit array to perform analog image processing tasks on-chip. The array is capable of real-time spatial and temporal filtering, as well as edge and/or motion enhancement effects. Each cell in the array includes bump pads for bonding the array to HgCdTe LWIR detector arrays, as well as visible light photo-transistors for testing the chip's functionality prior to hybridization.

An on-line recursive algorithm for training support vector machines, one vector at a time, is presented. Adiabatic increments retain the Kuhn(cid:173) Tucker conditions on all previously seen training data, in a number of steps each computed analytically. The incremental procedure is re(cid:173) versible, and decremental "unlearning" offers an efficient method to ex(cid:173) actly evaluate leave-one-out generalization performance. Interpretation of decremental unlearning in feature space sheds light on the relationship between generalization and geometry of the data.

Phase distortion in wavefront propagation is one of the key problems in optical imaging and laser optics applications. We present a hybrid VLSI and optical system for real-time adaptive phase distortion compensation. The system operates "model-free", independent of the specifics of the distorting optical medium and the compensation control elements. Our VLSI system implements stochastic parallel perturbative gradient descent/ascent so that we achieve fast optimization of the chosen performance metric to achieve real-time compensation. We include experimental results of the hybrid VLSI-optical system demonstrating successful operation for a laser-beam focusing/defocusing task.

The goal of this work is to augment reinforcement learning techniques for autonomous robot navigation with a state space encoding more representative of the actual state of the robot in its environment, than available from direct sensor readings. A second goal is to demonstrate the approach in a real-world setting, using the microrobot Khepera (K-Team, Lausanne, Switzerland). The choice of state representation is one of the most critical factors in the performance of reinforcement learning algorithms. The technique of inferring relative positional information indirectly from sensor readings, through unsupervised learning, is an important novel contribution of this work. As demonstrated in the robot experiments, the technique allows to optimally perform sensor fusion and avoids the need of more elaborate sensors conveying explicit information on position coordinates.

We present the design of neuromorphic CMOS integrated circuit imager arrays that performs analog computation on-chip prior to conventional off-chip digitizing. These imagers are capable of performing real-time nonuniformity correction using Scribner's scene-based nonuniformity correction (SBNUC) algorithm and can therefore learn to cancel the offsets of the sensor array dynamically.

We have developed a low power analog VLSI chip for real time signal processing motivated by the principles of the human auditory system. An analog cochlear filter bank (which is implemented on the chip) decomposes the input audio signal into several frequency bands that have almost equal bandwidth on a log scale. This step is thus similar to computing the wavelet transform. The chip then computes signal energies and zero crossing time intervals of frequency components in a cochlear filter bank. The chip is intended to work as a front-end of a speech recognition system. We include experimental results on a VLSI implementation of the auditory front-end. We present speech recognition results on the TI-DIGITS database obtained from computer simulations which model the functionality of the feature extraction VLSI hardware. We use hidden Markov models (HMM) in combination with linear discriminant analysis (LDA) for the recognizer design.

Real-time algorithms for gradient descent supervised learning in recurrent dynamical neural networks fail to support scalable VLSI implementation, due to their complexity which grows sharply with the network dimension. We present an alternative implementation in analog VLSI, which employs a stochastic perturbation algorithm to observe the gradient of the error index directly on the network in random directions of the parameter space, thereby avoiding the tedious task of deriving the gradient from an explicit model of the network dynamics. The network contains six fully recurrent neurons with continuous-time dynamics, providing 42 free parameters which comprise connection strengths and thresholds. The chip implementing the network includes local provisions supporting both the learning and storage of the parameters, integrated in a scalable architecture which can be readily expanded for applications of learning recurrent dynamical networks requiring larger dimensionality. We describe and characterize the functional elements comprising the implemented recurrent network and integrated learning system, and include experimental results obtained from training the network to represent a quadrature-phase oscillator.

An architecture is described for the microelectronic implementation of arbitrary outer-product learning rules in analog floating-gate CMOS matrix-vector multiplier networks. The weights are stored permanently on floating gates and are updated under uniform UV illumination with a general incremental analog four-quadrant outer-product learning scheme, performed locally on-chip by a single transistor per matrix element on average. From the mechanism of floating gate relaxation under UV radiation, the authors derive the learning parameters and their dependence on the illumination level and circuit parameters. It is shown that the weight increments consists of two parts: one term contains the outer product of two externally applied learning vectors; the other part represents a uniform weight decay, with time constant originating from the floating gate relaxation. The authors address the implementation of supervised and unsupervised learning algorithms with emphasis on the delta rule. Experimental results from a simple implementation of the delta rule on an 8x7 linear network are included.